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推动RISC-V芯片设计革命,第五届RISC-V中国峰会EDA分论坛干货满满
Guan Cha Zhe Wang· 2025-07-18 09:09
Core Insights - The fifth RISC-V China Summit will be held from July 16 to 19, 2025, in Shanghai, featuring a main forum, nine vertical sub-forums, five workshops, and a 4,500 square meter technology exhibition area, attracting hundreds of companies, research institutions, and open-source technology communities [1] Group 1: Siemens EDA and Debugging Solutions - Siemens EDA introduced Tessent UltraSight-V, a debugging and tracing solution specifically designed for RISC-V systems, addressing inefficiencies and high costs associated with traditional debugging methods [4] - Tessent UltraSight-V offers comprehensive end-to-end debugging and tracing capabilities, supporting various communication interfaces and mainstream development environments, significantly enhancing debugging efficiency [4][5] - Key features include efficient debugging functions, advanced tracing capabilities, scalability for single-core to multi-chip designs, and integration with UVM verification environments [5] Group 2: Chipmunk Technology and Simulation Optimization - Chipmunk Technology presented the "Near Cycle Model," a SystemC-based CPU modeling technology aimed at optimizing the simulation accuracy and performance of RISC-V processors [7] - The model integrates cycle information into simulations, significantly improving accuracy and enabling precise software performance evaluations, addressing limitations of traditional RISC-V simulation tools [7][8] - The technology supports seamless integration with third-party virtual platforms, allowing users to customize and deploy simulation configurations quickly [8] Group 3: Andes Technology and Custom Instruction Development - Andes Technology showcased the ACE framework and AndesCycle simulator to accelerate the development of custom instructions for RISC-V architecture [9] - The ACE framework simplifies the design process by allowing developers to generate hardware RTL code from two design files, enhancing development efficiency [11] - The AndesCycle simulator provides detailed instruction cycle analysis, helping developers identify and optimize performance bottlenecks, with real-world applications demonstrating significant performance improvements [12]