楠菲微电子董事长、控股股东为曾雨。曾雨直接持股17.82%，与其控制主体及一致行动人合计可控制该公司48.92%的股份表决权。 国家企业信用信息公示系统显示，2025年12月26日，楠菲微电子注册资本由3.4亿元变更为4.14亿元，增幅为21.79%。 | 序号 | 变更事项 | 变更前内容 | 变更后内容 | | --- | --- | --- | --- | | | 其他事项备案 | 価槽 | 林强 | | 2 | 高级管理人员备案(董事、监事、经 | 张磊:副总经理;王震:副总经理;倪正清:上市公司 董事会秘书,副总经理,财务负责人;管剑波:副总 | 张磊:副总经理;王震:副总经理;倪正清:上市公司 董事会秘书,财务负责人,副总经理;王克非:经理; | | | 理等) | 经理;王克非:经理;张鹤颖:副总经理 收起 | 张鹤颖:副总经理 收起 | | 3 | 注册资本变更(注册资金、资金数额 等变更) | 34000万人民币 | 41407.4074万人民币 | | 4 | 章程备案 | 2025-11-15 | 2025-12-25 | | 5 | 高级管理人员备案(董事、监事、经 理等) | 王克非 ...

Listing Announcement - Binance Alpha 将于 7 月 26 日上线 DePHY Network (PHY) [1] - 符合条件的用户可以在交易开放后使用 Binance Alpha Points 在 Alpha Events 页面上领取空投 [1] User Engagement - 更多详细信息将很快公布 [1] - 请关注 Binance 官方渠道以获取最新更新 [1]

Listing Announcement - Binance Alpha 将于 7 月 26 日上线 DePHY Network (PHY) [1] - 符合条件的用户可以在交易开放后使用 Binance Alpha Points 在 Alpha Events 页面上领取空投 [1] User Engagement - 更多细节将很快公布 [1] - 请关注 Binance 官方渠道以获取最新更新 [1]

Core Viewpoint - The article emphasizes the critical role of the physical layer (PHY) in data communication, particularly in the context of emerging technologies such as artificial intelligence and high-performance computing, highlighting its importance in meeting the increasing demands for bandwidth, low latency, and energy efficiency [3][6][11]. Summary by Sections Importance of PHY - The physical layer has evolved from supporting traditional industries to becoming foundational for AI factories and large-scale data centers, acting as a key driver for data transmission and communication [3]. - As data centers handle massive amounts of data, the significance of PHY increases, especially for AI and HPC workloads that require unprecedented system performance [3][6]. Standards and Applications - Understanding the physical layer is crucial for maintaining competitiveness in various applications, with different standards developed to address specific issues [4]. - Standards like HDMI and DisplayPort illustrate the need for compatibility and efficiency in system design, balancing cost and functionality [5]. Design Challenges - Designing PHY for speeds exceeding 100G presents numerous challenges, including process technology dependence, signal integrity, system design constraints, and packaging integration [8]. - The transition from NRZ to PAM signaling represents a significant shift in technology, necessitating advanced design techniques to meet increasing bandwidth demands [7][8]. Chip-to-Chip Communication - The development of chip-to-chip communication standards, such as UCIe, aims to achieve high bandwidth with low power consumption, which is essential for modern 3D systems [9]. - The integration of multiple dies in a system-on-chip (SoC) architecture requires careful consideration of physical layer protocols to optimize performance [9][10]. Collaboration Between Disciplines - Effective collaboration between analog and digital engineers is necessary to bridge the gap between different domains, ensuring that physical effects are adequately addressed in system design [10][11]. - A comprehensive understanding of how physical effects impact system performance is vital for optimizing designs and achieving desired outcomes [11]. Future Outlook - As the industry progresses towards higher standards like 448G, the challenges will intensify, particularly with the emergence of chip decomposition and optical I/O [11]. - The PHY layer is increasingly viewed as a strategic enabler, necessitating continuous innovation and commitment to pushing technological boundaries [11].