Financial Data and Key Metrics Changes - The company achieved record annual revenue of $7.05 billion, up approximately 15% year-over-year, with Q4 revenue of $2.25 billion, at the high end of guidance [5][14]. - The total backlog increased to $11.4 billion, up from $10.1 billion in the previous quarter [13]. - Non-GAAP operating margin for FY25 was 37.3%, with Q4 non-GAAP operating margin at 36.5% [14][15]. - GAAP earnings per share for Q4 and FY25 were $2.39 and $8.07 respectively, while non-GAAP earnings per share were $2.90 and $12.91, exceeding guidance [14][15]. Business Line Data and Key Metrics Changes - The design automation segment revenue, including EDA and Ansys, was $5.3 billion, up 26%, while excluding Ansys, it grew approximately 8% [15]. - The design IP segment revenue was $1.75 billion, down 8% due to challenges in the second half of the year [15]. - The hardware-assisted verification (HAV) business saw a record year with 12 competitive wins in Q4 [8]. Market Data and Key Metrics Changes - China faced significant challenges, with revenue down 18% for FY25, and down 22% excluding Ansys [14]. - The company noted stronger semiconductor demand in mobile and automotive sectors, while industrial markets remained subdued [6]. Company Strategy and Development Direction - The integration of Ansys is a key focus, with the company aiming to deliver joint solutions in the first half of 2026 [11][62]. - The company is targeting double-digit growth for Ansys revenue in FY26, driven by increased R&D investments in various industries [60]. - A strategic partnership with NVIDIA is expected to enhance design and engineering capabilities with AI and accelerated computing [7]. Management's Comments on Operating Environment and Future Outlook - Management expressed optimism about the long-term growth potential despite current challenges, particularly in the IP business [41][76]. - The company is adopting a pragmatic approach to forecasting, particularly regarding the ongoing challenges in China [76]. - Management emphasized the importance of AI in driving future demand for engineering solutions, indicating a shift in how engineering is approached [6][48]. Other Important Information - The company plans to prepay $2.55 billion of its term loans in the first half of 2026, which is expected to be accretive to EPS [16][19]. - The guidance for FY26 includes total revenue of $9.56-$9.66 billion, with Ansys contributing approximately $2.9 billion at the midpoint [17]. Q&A Session Summary Question: What is the embedded organic growth rate in the 2026 guide? - Management indicated it is around 8%, factoring in the divestitures and muted growth expectations for the IP business [22][23]. Question: What are the expectations for EDA and IP growth in the guidance? - Management acknowledged that EDA growth is impacted by the China environment and a muted roadmap for certain customers, while IP is expected to have a transitional year [31][32]. Question: Can the IP business achieve mid-teens growth in FY27? - Management expressed confidence in the IP portfolio and ongoing customer engagements, indicating that growth could return to mid-teens in the future [82]. Question: What is the rationale behind the NVIDIA investment? - The investment was made to accelerate computational capabilities and modernize engineering solutions, leveraging the strengths of both companies [44][45]. Question: How is the integration of Ansys progressing? - Integration efforts are underway, with R&D teams working together to deliver joint solutions, while maintaining separate go-to-market strategies for different customer segments [61][62].

Financial Data and Key Metrics Changes - Synopsys achieved record annual revenue of $7.05 billion in FY25, up approximately 15% year-over-year, with Q4 revenue of $2.25 billion, aligning with guidance [12][13] - The company ended FY25 with a backlog of $11.4 billion, up from $10.1 billion in the previous quarter [12] - Non-GAAP operating margin for FY25 was 37.3%, with Q4 non-GAAP operating margin at 36.5% [14] - GAAP earnings per share for FY25 were $8.07, while non-GAAP EPS was $12.91, exceeding guidance due to lower expenses [14][15] Business Line Data and Key Metrics Changes - The design automation segment, including EDA and Ansys, generated $5.3 billion in revenue for FY25, up 26%, while excluding Ansys, it grew approximately 8% [15] - The design IP segment revenue was $1.75 billion, down 8% due to challenges in the second half of the year [15] - Ansys contributed $757 million to total revenue in FY25, with Q4 revenue of $668 million [13][14] Market Data and Key Metrics Changes - China faced significant challenges, with revenue down 18% in FY25, and excluding Ansys, down 22% [13][14] - The semiconductor demand is strong in mobile and automotive sectors, while industrial markets remain subdued [5][12] Company Strategy and Development Direction - Synopsys aims to leverage the Ansys acquisition to enhance its engineering solutions from silicon to systems, focusing on AI-driven design and multi-domain integration [4][6] - The company plans to deliver its first joint solutions with Ansys in the first half of 2026, targeting double-digit growth for Ansys revenue [11][56] - Strategic partnerships, such as with NVIDIA, are expected to enhance design and engineering capabilities [6][40] Management's Comments on Operating Environment and Future Outlook - Management expressed optimism about the AI infrastructure build-out driving semiconductor demand, despite challenges in certain markets like China [5][12] - The company anticipates a transitional year for the IP business in FY26, with muted growth expected due to ongoing adjustments and market conditions [10][36] - Management emphasized a focus on operational excellence and financial discipline to drive sustainable growth and margin expansion [11][19] Other Important Information - Synopsys plans to prepay $2.55 billion of its term loans in the first half of 2026, which is expected to be accretive to EPS [16][18] - The company is adopting a normalized non-GAAP tax rate of 18% projected through 2028 [17] Q&A Session Summary Question: What is the embedded organic growth rate in the 2026 guide? - Management indicated that the organic growth rate is around 8%, factoring in the divestitures and muted growth for the IP business [22][23] Question: What are the growth expectations for EDA and IP in the guidance? - Management confirmed that EDA growth is impacted by the China environment and ongoing market dynamics, with IP expected to grow modestly [28][29] Question: Can you provide an update on the IP business and headwinds? - Management acknowledged challenges in the IP business but expressed confidence in long-term growth, emphasizing ongoing customer engagement and portfolio strength [35][36] Question: What is the rationale behind the NVIDIA investment? - The investment was driven by the potential for accelerated computational capabilities and modernization of engineering solutions, enhancing market reach [40][41] Question: How does the company plan to address the monetization challenges in EDA? - Management recognized the need for better monetization strategies and highlighted the importance of joint solutions with Ansys to capture value [78][80]

Core Viewpoint - Synopsys (SNPS) stock has experienced a significant decline of 25.3% over the past three months, underperforming the Zacks Computer - Software industry, which returned 1.4% during the same period. This raises questions about whether investors should hold or exit the stock [1][8]. Group 1: Growth Prospects - Synopsys is focusing on AI-driven electronic design automation (EDA) tools, such as Synopsys.ai and Fusion Compiler, which are being rapidly adopted by customers, leading to substantial productivity gains [4]. - The company is expanding into the AI cluster interconnect market with new products like Ultra Accelerator Link and Ultra Ethernet IP solutions, benefiting from the projected growth of the Data Center Interconnect market, expected to reach $25.89 billion by 2030, with an 11% CAGR from 2025 to 2030 [5]. - The Zacks Consensus Estimate for Synopsys' fiscal 2025 revenues is $7.05 billion, indicating a year-over-year growth of 12.5% [9]. Group 2: Market Challenges - Synopsys faces significant competition from companies like Broadcom and Marvell Technology, as well as EDA vendors such as Cadence Design Systems and Siemens, which are challenging its market position [10][12][13]. - The Design IP business of Synopsys has declined by 8% year-over-year due to delays from foundry customers and internal resource allocation issues, leading to a muted outlook for fiscal 2026 [17]. - Operating margins are under pressure due to weakness in the Design IP business and geopolitical risks, particularly in China, which are affecting the business outlook [18]. Group 3: Valuation Concerns - Synopsys is currently trading at a premium valuation, with a forward 12-month price-to-sales (P/S) ratio of 8.83X, higher than the industry average of 8.54X, contributing to a Zacks Value Score of F [20]. - The Zacks Consensus Estimate for fiscal 2025 earnings is $12.8 billion, indicating a year-over-year decline of 2.8% [14]. Group 4: Conclusion - Given the combination of high valuation, declining margins, increasing competition, and challenges in the Design IP business, it is suggested that investors consider selling SNPS stock [21].

Core Insights - Synopsys' AI-driven electronic design automation (EDA) tools are experiencing rapid adoption, leading to significant productivity gains for customers [1] - The company has established strong partnerships with various firms, including Advanced Micro Devices and Toshiba, indicating its growing influence in the EDA market [1] - Synopsys' software-based verification tools are increasingly utilized by both traditional semiconductor and emerging system companies, driven by the need for precise verification in advanced nodes [2] Company Developments - The implementation of the ZeBu Server 4 design emulation system by AI-chip developers is enhancing System-on-Chip (SoC) verification processes [3] - Synopsys has expanded its capabilities in the SoC verification and IP space through the acquisition of Intrinsic ID, which enhances security by generating unique identifiers for SoCs [4] - Recent acquisitions, including ANSYS, are expected to create synergies that strengthen Synopsys' EDA offerings [3][4] Competitive Landscape - Synopsys faces competition from EDA vendors like Cadence Design Systems and Siemens, which offer similar tools and services for chip design [5][6] - These competitors focus on different phases of the integrated circuit (IC) design process, potentially increasing competition and impacting Synopsys' pricing and profit margins [6] Financial Performance - Synopsys shares have declined by 8.5% year-to-date, contrasting with a 19.8% growth in the Computer - Software industry [7] - The company's forward price-to-sales ratio stands at 8.58X, slightly above the industry average of 8.55X [9] - Earnings estimates for fiscal 2025 indicate a year-over-year decline of 2.8%, while estimates for 2026 suggest a growth of 9.5% [10]

Core Viewpoint - The article discusses the launch of LibreLane, a successor to OpenLane, designed for open-source chip design, emphasizing its enhanced flexibility and usability in ASIC processes [3][4]. Group 1: LibreLane Overview - LibreLane is a complete redesign of OpenLane, allowing for customizable and distributable ASIC processes using a Python-based infrastructure [3]. - The default Classic flow in LibreLane closely replicates OpenLane, supporting the same configuration files while enabling users to create fully custom high-level data flows [3][4]. Group 2: Development and Goals - The development of LibreLane was initiated by a team from the now-defunct eFabless company, aiming to maintain OpenLane's configuration files while providing greater flexibility and consistency [4]. - The core philosophy of LibreLane is to clearly represent the current state of design, storing various file paths and metrics in immutable objects for traceability [4][5]. Group 3: EDA Task Modeling - EDA tasks are modeled as functions that receive a state and output another state, allowing for high repeatability and parallel exploration of configurations [5]. - Processes in LibreLane can be simple sequential flows or fully customized functions, facilitating easier command-line control and execution [5][6]. Group 4: Configuration and Integration - The Config module in LibreLane allows users to configure processes using Tcl, JSON, or YAML files, addressing previous pain points in input validation and type checking [6]. - LibreLane supports integration with other tools, enhancing performance in chip design by combining with Synopsys Design Compiler and PrimeTime tools [6]. Group 5: Adoption and Future Prospects - Tiny Tapeout utilizes LibreLane for its custom processes, and ChipFoundry has agreed to adopt LibreLane as its primary process, continuing the legacy of OpenLane in commercializing open-source EDA technology [7]. - The first version of LibreLane, 2.4.0, is available for macOS and Linux, with installation guides provided for users [7].