Core Viewpoint - Intel and UMC are entering a significant collaboration, where Intel will license its exclusive Super MIM technology for next-generation advanced packaging and process nodes, marking a new milestone in US-Taiwan semiconductor cooperation [1] Group 1: Collaboration Details - The current focus of the collaboration is on the 12nm platform, with potential for expanding into more diverse technology areas in the future [1] - UMC has established a dedicated team to initiate this new collaboration, while Intel has not commented on the matter [1] Group 2: Super MIM Technology - Super MIM technology utilizes materials such as HfO2, TiO2, and STO to significantly enhance capacitance density while reducing leakage current, addressing the limitations of traditional decoupling capacitors [2] - This technology is crucial for providing instantaneous current support within chips, suppressing voltage droop and power noise, and is considered a key power module for the successful mass production of advanced nodes like 18A [2] Group 3: Implications for UMC - By acquiring Intel's Super MIM technology, UMC can advance its capabilities in power technology and establish a differentiated technological barrier in mature advanced processes and packaging [2] - Successful implementation of Super MIM will not only optimize a single process but also provide UMC with a cross-generational capability in advanced power modules, facilitating entry into high-value applications such as AI accelerators and advanced packaging power layers [2]

Core Viewpoint - The introduction of Backside Power Delivery Network (BSPDN) by major semiconductor companies like Intel and TSMC is a significant advancement in semiconductor technology, aimed at addressing the limitations of traditional chip designs and extending Moore's Law [2][4]. Group 1: What is Backside Power Delivery? - BSPDN is considered a breakthrough that continues Moore's Law, improving heat dissipation, reducing IR drop, and increasing chip density [4]. - Traditional chip designs concentrate power and signal lines on the front of the wafer, which becomes problematic as advanced processes approach 2nm and below [5]. Group 2: Importance of Backside Power Delivery - Reduces voltage drop and power loss, ensuring stable power supply during high-speed AI computations and server applications [6]. - Addresses thermal bottlenecks and IR drop issues caused by lengthy circuits, which can lead to operational errors or performance degradation [7]. - Enhances performance by separating power and signal, thereby reducing interference [8]. Group 3: Global Strategies for Backside Power Delivery - Three main solutions are currently being developed: imec's Buried Power Rail, Intel's PowerVia, and TSMC's Super Power Rail [10]. - imec is a leader in BSPDN technology, having published its findings in collaboration with Arm in 2022, utilizing BPR and nTSV architecture [11]. - Intel plans to implement BSPDN in its 18A process, expected to enter mass production in late 2025, focusing on complete separation of power and signal [11]. - Samsung will introduce BSPDN technology in its SF2Z process, with mass production anticipated in 2027 [12]. - TSMC's approach involves using Super Power Rail to direct power to the front transistors, which is crucial for maintaining its competitive edge in advanced processes [13]. Group 4: Implications for the Semiconductor Industry - BSPDN is seen as a key technology for extending Moore's Law, especially as traditional methods of shrinking transistors face limitations [15]. - The competition among major players to mature and commercialize this technology will determine their influence in the semiconductor industry over the next decade [13].