Core Viewpoint - SJ Semiconductor Corporation (盛合晶微) has successfully passed the listing review by the Shanghai Stock Exchange, marking a significant milestone in its IPO process as a leading advanced packaging enterprise in the semiconductor industry [1] Group 1: Company Overview - SJ Semiconductor is recognized as a global leader in integrated circuit wafer-level advanced packaging, with notable technological barriers and scale advantages in mid-silicon wafer processing, wafer-level packaging, and multi-chip integration packaging [1] - The company is projected to achieve a revenue of 6.521 billion yuan in 2025, representing a year-on-year growth of 38.59%, and a net profit of 923 million yuan, reflecting a substantial year-on-year increase of 331.80% [1] Group 2: IPO and Fundraising - The company plans to raise 4.8 billion yuan through its IPO to expand its core business in 3D packaging, indicating a broad valuation and market capitalization potential post-listing [1] Group 3: Shareholder Information - *ST Yushun (ST宇顺) indirectly holds approximately 330.72 thousand shares of SJ Semiconductor, corresponding to a holding ratio of about 0.206% [4] - *ST Yushun has invested in the Yuanhe Changxin No. 2 Venture Capital Partnership, holding about 7.80% of the fund, which in turn owns 42.4 million shares of SJ Semiconductor, making it the fifth-largest shareholder [2][3] - The investment in SJ Semiconductor is expected to yield significant asset appreciation for *ST Yushun as the company progresses with its IPO [4]

Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. has entered the inquiry stage for its IPO on the Sci-Tech Innovation Board, aiming to raise approximately 4.8 billion yuan for advanced packaging projects [1] Company Overview - Shenghe Jingwei is an advanced packaging enterprise specializing in integrated circuit wafer-level packaging [1] - The company’s IPO application was accepted on October 30, 2025 [1] Fundraising Purpose - The funds raised from the IPO will be allocated to a three-dimensional multi-chip integration packaging project and an ultra-high-density interconnection three-dimensional multi-chip integration packaging project [1]