Welcome to part two of the Modular NoCs series. In this video, you are going to learn about how to add XPMs into your design to utilize the modular NoC. To refresh your memory, the modular NoC solution is comprised of three main steps.Step one is to connect all AXI busses that want to utilize the NoC to Xilinx parameterizable macros or XPMs. . The second step of the process is to add constraint files (or XDCs) to the design that define connectivity and quality of service parameters for each individual NoC c ...

Welcome to part four of the modular NoC series. In this video, you're going to learn about the validate_noc command. At this stage, we know how to connect all AXI busses by utilizing XPMs and how to define multiple constraints like connectivity addressing QoS and bandwidth by using constraint files (or XDCs).The final step in this three step process is to run the validate_noc command. This video focuses on this command. The validate_noc command validates the NoC topology for the entire system. The validate_ ...

Modular NoC Solution Overview - The modular NoC solution involves connecting AXI busses to Xilinx parameterizable macros (XPMs), adding constraint files (XDCs) to define connectivity and quality of service (QoS) parameters, and running the validate NoC command [2] - The focus is on adding constraint files (XDCs) to define connectivity and QoS parameters for each NoC connection [3] XDC Constraint File Configuration - XDC files can be specified per module and do not require RTL elaboration when modified [4] - The XDC file defines the addressing aperture of the NSU, ensuring addresses are routed appropriately; if the NSU is in the block design, the aperture is defined in the BD and doesn't need specification in the XDC [6] - The XDC file creates NoC connections between NMUs and NSUs and applies QoS constraints to those connections [7] - Setting the USED_IN property of the XDC file to "synthesis_pre" is necessary for the validation command to find the NoC constraints [10] Creating NoC Connections - The "get_noc_interfaces" command is used to get a list of available NoC interfaces in the design [11] - The "create_noc_connection" command is used to create connections between NMUs and NSUs [12][15] - The "set_property" command is used to specify QoS properties like READ_BANDWIDTH, READ_AVERAGE_BURST, WRITE_BANDWIDTH, and WRITE_AVERAGE_BURST, as well as TDEST_IDs for the connections [15][16]

Products & Technologies - Modular NoC in a DFX design flow is highlighted [1] - Vivado for Versal adaptive SoCs and FPGAs is mentioned [1] Community & Social Media - Encourages users to subscribe to AMD [1] - Promotes joining the AMD Red Team Community [1] - Invites users to the AMD Red Team Discord Server [1] - Lists AMD's presence on Facebook, Twitter, Twitch, LinkedIn, and Instagram [1] Legal & Copyright - ©2025 Advanced Micro Devices, Inc [1] - Mentions AMD trademarks and other trademarks for informational purposes [1]

My name is Mark Wallis. I work for the ISG group at Lenovo, and I'm here to talk about how AMD and Lenovo work together to bring telco solutions. I have in front of me here, this is the latest 5th gen AMD server.It's called the SR645. It's a dual socket, Zen5C system. This has only just been released.We've released some 17 SKUs very recently on AMD. And we actually hold the world spec power record on AMD using one of these CPUs, the 9845 CPU, on this exact server. This is the dual socket server, and we're h ...

Product Overview - Nokia, AMD, and Hewlett Packard collaborated to create an appliance product line featuring a two-server solution [1] - The appliance deploys Nokia's Packet Core products (control plane and user plane) as VNFs on AMD servers with a lightweight KVM infrastructure [2] - This approach avoids the need for a full OpenStack deployment, reducing the number of servers and infrastructure costs [2][3] - Local automation, deployment, and software updates are managed with Python scripts [3] Performance and Capacity - AMD chipsets provide 30% better performance compared to other systems [4] - Future AMD systems (Gen12) are expected to support over 400 gigabits per second (Gbps) of FWA capacity in a two-server system [5] Target Applications and Value Proposition - Initially intended for edge deployment at service operator customer enterprise locations [3] - Reduced TCO due to fewer servers and lower infrastructure costs makes it suitable for mainstream applications [4] - The solution is valid for both FWA and mobile broadband applications [5]

Product & Technology - Supermicro and AMD collaborate to provide advanced and energy-efficient solutions for training, inferencing, edge computing, and telco applications [1] - Supermicro offers liquid-cooled systems for AI training and inferencing, supporting Turin and Genoa processors, as well as MI300X and MI325X GPUs [2] - Supermicro also provides air-cooled systems based on Turin processors and MI325X GPUs [2] - Supermicro's 8-way system is the highest-performing platform based on AMD [3] - Supermicro offers compute and storage platforms based on Turin processors, supporting high-frequency, medium-core count (32 or 64 cores), and massive core count applications in 1U and 2U form factors [4] - Supermicro's storage solutions leverage 128 lanes of PCI Express Gen 5 for high performance [5] Market Focus - Supermicro provides platforms for standard compute and storage, catering to various ISVs for scale-out and standard storage [5] - Supermicro offers platforms suitable for AI, standard compute, and storage, with options for air-cooled or liquid-cooled systems [6] - Supermicro emphasizes efficient and fast time-to-market solutions [6]

Performance Improvement - AMD's 5th generation EPYC offers a 75% performance uplift compared to the 4th generation in Ericsson packet core solutions [1] - AMD's solutions provide a 40% power efficiency benefit generationally [2] Partnerships and Solutions - Ericsson's packet core is available on both 4th and 5th generation AMD EPYC [1] - Nokia appliance on AMD packet core is available on 2nd, 4th and 5th generation EPYC [2] - ZTE offers packet core solutions [2] Market Presence - AMD is showcasing packet core solutions at MWC 2025 [1] - Ericsson and Nokia are exhibiting their solutions at MWC [1][2]

Industry Focus & Participation - The Mobile World Congress (MWC) is a key event for the telecommunications industry [1] - AMD has a diverse product portfolio enabling participation with OEMs, packet core providers, and operators in the telecommunications sector [1] Partnership & Technology - AMD collaborates with KDDI at MWC, showcasing technologies in life transformation [2] - The collaboration between AMD and KDDI utilizes AMD EPYC technology [3] - The partnership leverages AMD EPYC technology for its performance capabilities [3]

AMD's EPYC CPU in Telecommunications - AMD focuses on telecommunications with its EPYC CPU product line, showcasing innovations in packet core and RAM [1] - AMD has been collaborating with Ericsson and Nokia for over two years on multiple CPU generations [1] Value Proposition - AMD's EPYC CPUs offer a high core count, enabling significant throughput and reduced power consumption in the packet core [2] - Lower power consumption is particularly important for European carriers focused on sustainability [2] - AMD's fourth-generation product, Sienna, is an optimal edge platform that supports software-only RAM [3] - Sienna eliminates the need for accelerators, simplifying the Bill of Materials (BOM) [4] - This simplified BOM aligns with the goals of open RAN and NFV (Network Functions Virtualization) [4] Market & Partnership - Telecommunications industry regulations and testing certifications cause slow deployment [5] - AMD is starting to see real network deployments with major carriers, underpinned by partnerships with TEMs (Telecom Equipment Manufacturers) [5]