Event Overview - AMD is hosting a Public Sector Summit to provide insights and foster collaboration [1] - The summit's goals, themes, and key sessions will be introduced in the welcome message [1] AMD Resources - AMD encourages viewers to subscribe to their content [1] - AMD invites users to join the AMD Red Team Discord server [1] - AMD maintains a presence on various social media platforms including Facebook, Twitter, Twitch, LinkedIn, and Instagram [1] Legal and Trademark Information - The document acknowledges AMD's trademarks and copyrights, including the AMD Arrow Logo [1] - Other names mentioned are for informational purposes and may be trademarks of their respective owners [1] - The document is copyrighted to 2025 Advanced Micro Devices, Inc [1]

ADAS技术与应用 - ADAS系统通过摄像头、雷达和激光雷达等传感器收集数据，用于实现碰撞避免、自动驾驶、泊车辅助等功能 [1] - 实时感知和通信对于在互联车辆和道路基础设施之间无缝协调ADAS至关重要 [2] 行业挑战与需求 - 汽车制造商面临着在提高AI计算处理性能的同时，降低车辆电池功耗的挑战 [2] - 汽车安全标准对严苛驾驶条件下的高可靠性有要求，影响散热和封装需求 [3] - 灵活的解决方案对于适应不断发展的ADAS平台至关重要 [3] AMD解决方案与优势 - AMD提供可扩展的解决方案，以平衡性能、功耗和成本，并提供广泛的集成选项 [3] - AMD技术已在汽车行业应用超过15年，ADAS创新持续发展 [3]

ADAS Features & Technologies - ADAS systems enhance safety and driver experience in AI-enhanced vehicles by utilizing data from cameras, radar, and LiDAR [1] - These systems enable features like collision avoidance, automated parking assist, driver monitoring, and object detection [1] - Real-time sensing and communication are vital for seamless ADAS operation across interconnected vehicles and infrastructure [2] Challenges & Requirements - Automakers face the challenge of harnessing increased AI processing performance while conserving vehicle battery power [2] - Automotive safety standards necessitate high reliability in harsh driving conditions, impacting thermal and packaging requirements [2] AMD Solutions - AMD offers scalable processing solutions to balance performance, power, and cost for evolving ADAS platforms [3] - AMD technologies have been deployed in the automotive industry for over 15 years [3]

At AMD solving the world's most important challenges starts with investing in what's really important. From scientific research and STEM education to responsibility across our operations supply chain and products. From fostering an inclusive workforce where innovation is free to thrive to nurturing our communities cultures and connections.Together we advance technology. And together we can advance humanity. ...

AI Edge Computing Leadership - AMD empowers developers and engineers to unlock the full potential of AI at the edge [1] - AMD's embedded portfolio accelerates insights from data, enabling real-time decision-making [1] - AMD's solutions maximize productivity and innovation across various industries including industrial, healthcare, space, and automotive [1] Product Portfolio - AMD offers adaptive SoCs and x86 processor solutions for embedded computing [1] Marketing and Community Engagement - AMD encourages viewers to subscribe to their YouTube channel [1] - AMD invites users to join the AMD Red Team Discord Server [1] - AMD lists various social media platforms for users to follow [1] Legal and Trademark Information - The content is copyrighted to 2025 Advanced Micro Devices, Inc [1] - AMD, the AMD Arrow Logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc in the United States and other jurisdictions [1]

Overview - The Vitis Unified IDE is a development environment for AMD Adaptive SoCs and FPGAs application creation [1] - The video demonstrates the Vitis Embedded development flow and navigating the new Vitis Unified IDE [1] Development Process - Creating the platform and a "hello world" application within the Vitis Unified IDE [1] - Setting up target connections and deploying on the target board [1]

Software Development & FPGA Acceleration - Vitis HLS 2023.1 introduces a new L1 library wizard [1] - The wizard facilitates downloading, viewing, and instantiating L1 library functions within the Vitis HLS GUI [1] - The report focuses on learning about Vitis L1 libraries [1]

AI Engine Rapid Prototyping Overview - AMD introduces the Versal AI Engine Rapid Prototyping using the AMD Vitis Unified IDE for early design analysis and risk reduction [1][2][12][13] - The rapid prototyping feature is available in the Vitis Unified IDE in version 20242 [13][16] Key Steps in Rapid Prototyping - Involves resource estimation, including tile count, buffer usage, PLIO resources, and stream array traffic [2] - Assesses latency and throughput feasibility with early data flow simulations, prototype kernel coding, and initiation interval loop analysis [2] - Utilizes Vitis libraries for existing block elements and develops candidate vectorization options [3] - Includes building empty kernel wrappers, building the graph and compiling, simulating and analyzing for early estimation [12] Custom Kernel Example: Digital Up Conversion (DUC) Chain - The DUC chain translates a signal from baseband to intermediate frequency band and includes a FIR fractional resampler, half-band interpolators, DDS mixer functions, and an adder functional block [5] - The FIR fractional resampler, the half-band interpolators, and DDS mixer functions can be implemented using the Vitis DSP Library [5] - Focuses on fast prototyping of the custom adder kernel, identifying input/output data types, coefficient types, number of taps, sampling rate, and the kernel function [6] AI Engine System Mapping - Identifies hardware resources such as the number of AI Engine tiles, storage, buffers, and connectivity ports [8] - Considers compute (AIE tiles), storage (buffer size, local memory, DMA size), and input/output bandwidth (PLIO ports, clocking, buffer/stream interfaces) [8] - A custom adder kernel requires a sampling rate of 1200 MSPS with a latency less than 500 ns [9] - The adder is implemented in one tile with two inputs and one output of cint16 type, taking 3KB of data at a sampling rate of 1200 MSPS [10][11] Vitis Unified IDE Implementation - Generates data flow models with parametrized kernel ports, multi-core graph topology, full buffering, stream details, and LUT storages [14] - Allows exploration of hardware utilization through AI Engine compilation and ensures throughput and latency requirements are met through AI engine emulation [14] - Requires creating a new empty AI engine component and using the "Generate AIE Prototype Code" option [15] - Involves setting kernel properties such as name, input/output port properties (data type cint16, dimension to 384 samples), and enabling "Generate Top Level graph and Simulation code" [19][20] Simulation and Analysis - The tool generates graph CPP and H files, with the graph CPP setting the graph to run for one iteration (modifiable for better analysis) [20][21] - Requires adding input text files for simulation, containing values representing cint16 samples per clock on the 64-bit interface [22][23][24][25] - Simulation results report a throughput of 5000 megabytes/second or 1250 mega 16-bit complex samples per system, meeting the requirements [26]

Key Features of AMD Vitis Unified IDE - AMD Vitis Unified IDE utilizes Eclipse Theia framework, offering a modern and responsive GUI to enhance user experience [2] - The IDE supports a bottom-up design flow, enabling the development of system components like AI Engine graphs, C/C++ sourced HLS components, RTL kernels, and software applications [2] - It provides integrated revision control using Git and Python, along with a Tcl script-based interface for command-line component management [3] HLS Component Development - HLS component development is streamlined through a bottom-up design flow managed with a configuration file [3] - The IDE facilitates independent building, simulation, analysis, and debugging of HLS components [3] - Tools like component cloning allow for design optimization exploration, while component comparison provides insights into performance and resource utilization [4] - Code analyzer offers capabilities for architectural refinement [4] Migration Flows from Classic Vitis HLS - Migration from classic Vitis HLS designs to the Unified IDE is possible via GUI, command-line, and scripting [4] - In GUI, specify the hls app file from the classic Vitis HLS project when creating an HLS component [5] - For Tcl scripting, replace `open_project` with `open_component` and remove `open_solution`; specify `-flow_target` as either `vivado` or `vitis` [6] - Python APIs are available for creating and managing HLS components, with configuration specified in a file or directly in the script [8]

HLS Design Flow in Vitis Unified IDE - The AMD Vitis Unified IDE supports a bottom-up approach for heterogeneous system design, enabling the creation of individual system elements as components [2] - The IDE offers various development flows, including HLS, AI Engine Graph, Embedded, and System Development, along with tools for report analysis and user-managed workflows [2] - The Vitis Components view provides hierarchical project navigation, organizing source files and test benches [14] HLS Component Creation and Configuration - An HLS component can be created using the 'Create HLS Component' wizard, which guides users through the process [3] - The HLS component configuration file stores commands and settings for synthesis, simulation, and export [6] - Users can specify the top-level function to be synthesized, with underlying functions also synthesized into RTL [9] - The tool automatically applies uncertainty margin during synthesis to create RTL that is more likely to meet timing in Vivado [11] - The flow target can be set to either 'Vivado IP' or 'Vitis kernel', with the default 'Vivado IP' setting generating a .zip file [11][12] Verification and Packaging - C simulation can be run with default settings, generating a summary report and simulation log file [16][17] - RTL cosimulation verifies the generated RTL against the C test bench to ensure identical results [20] - The design can be packaged into a reusable IP component, with options for Vivado IP, Vitis kernel (.xo file), or RTL output [22][23][24][25] RTL Analysis and Implementation - HLS provides estimations for resource utilization and timing, but accurate RTL analysis requires running Vivado RTL synthesis and place-and-route [25][26] - Vivado synthesis and implementation can be configured before execution using the Implementation settings [26]