Overview - The video provides a brief introduction to the new ChipScoPy API [1]

Software Installation - The video guides the installation of the ChipScoPy API [1] - The installation process includes the official Python install [1] - It covers obtaining the latest version of the ChipScoPy API [1] - The video demonstrates installation on a Windows PC [1]

Overview - This video demonstrates how to obtain the Hardware Server and ChipScope Server from the Unified Installer [1] - This video demonstrates how to connect ChipScoPy to the VCK190 evaluation platform [1]

Challenges with Current NoC Solution - Current NoC IP requires all instances to be placed on a block design canvas, making the block design a bottleneck for teams modifying NoC connectivity or attributes [4][6] - Routing AXI busses through the RTL hierarchy is a tedious process [5][6] - Additional complications arise when considering DFX use cases [6] Modular NoC Solution Overview - The modular NoC solution allows the NoC to be distributed among various design sources and hierarchies, resolving issues with the current solution [7] - The solution comprises three main steps: connecting AXI busses to Xilinx Parameterizable Macros (XPMs), adding constraint files (XDCs) to define connectivity and QoS parameters, and executing the `validate_noc` command [7][9][10] - The `validate_noc` command ensures full connectivity between XPM instances, runs DRCs, and executes the NoC compiler to generate the NoC solution [10][21] Key Features and Benefits - Teams can develop solutions independently, and the tool ensures the NoC is not overcommitted [8][10] - The solution maintains compatibility with the current solution, and simulation, debug flows, Vitis Unified IDE, and system software support are unchanged [11] - The solution is designed with enough flexibility to accommodate future enhancements such as security and isolation features [12] Supported Use Cases - AXI Master in the RTL accessing a port of the DDR memory controller on the block design [25] - A master on the BD accessing a peripheral in the RTL [26] - An RTL master accessing peripherals of the processing subsystem [26] - RTL to RTL NoC transfers [27] Tutorials and Further Learning - A series of tutorials are available for download, covering foundational concepts, DFX basics, advanced NoC properties, advanced DFX topics, and HBM [30]

Welcome to part two of the Modular NoCs series. In this video, you are going to learn about how to add XPMs into your design to utilize the modular NoC. To refresh your memory, the modular NoC solution is comprised of three main steps.Step one is to connect all AXI busses that want to utilize the NoC to Xilinx parameterizable macros or XPMs. . The second step of the process is to add constraint files (or XDCs) to the design that define connectivity and quality of service parameters for each individual NoC c ...

Welcome to part four of the modular NoC series. In this video, you're going to learn about the validate_noc command. At this stage, we know how to connect all AXI busses by utilizing XPMs and how to define multiple constraints like connectivity addressing QoS and bandwidth by using constraint files (or XDCs).The final step in this three step process is to run the validate_noc command. This video focuses on this command. The validate_noc command validates the NoC topology for the entire system. The validate_ ...

Modular NoC Solution Overview - The modular NoC solution involves connecting AXI busses to Xilinx parameterizable macros (XPMs), adding constraint files (XDCs) to define connectivity and quality of service (QoS) parameters, and running the validate NoC command [2] - The focus is on adding constraint files (XDCs) to define connectivity and QoS parameters for each NoC connection [3] XDC Constraint File Configuration - XDC files can be specified per module and do not require RTL elaboration when modified [4] - The XDC file defines the addressing aperture of the NSU, ensuring addresses are routed appropriately; if the NSU is in the block design, the aperture is defined in the BD and doesn't need specification in the XDC [6] - The XDC file creates NoC connections between NMUs and NSUs and applies QoS constraints to those connections [7] - Setting the USED_IN property of the XDC file to "synthesis_pre" is necessary for the validation command to find the NoC constraints [10] Creating NoC Connections - The "get_noc_interfaces" command is used to get a list of available NoC interfaces in the design [11] - The "create_noc_connection" command is used to create connections between NMUs and NSUs [12][15] - The "set_property" command is used to specify QoS properties like READ_BANDWIDTH, READ_AVERAGE_BURST, WRITE_BANDWIDTH, and WRITE_AVERAGE_BURST, as well as TDEST_IDs for the connections [15][16]

Products & Technologies - Modular NoC in a DFX design flow is highlighted [1] - Vivado for Versal adaptive SoCs and FPGAs is mentioned [1] Community & Social Media - Encourages users to subscribe to AMD [1] - Promotes joining the AMD Red Team Community [1] - Invites users to the AMD Red Team Discord Server [1] - Lists AMD's presence on Facebook, Twitter, Twitch, LinkedIn, and Instagram [1] Legal & Copyright - ©2025 Advanced Micro Devices, Inc [1] - Mentions AMD trademarks and other trademarks for informational purposes [1]

My name is Mark Wallis. I work for the ISG group at Lenovo, and I'm here to talk about how AMD and Lenovo work together to bring telco solutions. I have in front of me here, this is the latest 5th gen AMD server.It's called the SR645. It's a dual socket, Zen5C system. This has only just been released.We've released some 17 SKUs very recently on AMD. And we actually hold the world spec power record on AMD using one of these CPUs, the 9845 CPU, on this exact server. This is the dual socket server, and we're h ...

Product Overview - Nokia, AMD, and Hewlett Packard collaborated to create an appliance product line featuring a two-server solution [1] - The appliance deploys Nokia's Packet Core products (control plane and user plane) as VNFs on AMD servers with a lightweight KVM infrastructure [2] - This approach avoids the need for a full OpenStack deployment, reducing the number of servers and infrastructure costs [2][3] - Local automation, deployment, and software updates are managed with Python scripts [3] Performance and Capacity - AMD chipsets provide 30% better performance compared to other systems [4] - Future AMD systems (Gen12) are expected to support over 400 gigabits per second (Gbps) of FWA capacity in a two-server system [5] Target Applications and Value Proposition - Initially intended for edge deployment at service operator customer enterprise locations [3] - Reduced TCO due to fewer servers and lower infrastructure costs makes it suitable for mainstream applications [4] - The solution is valid for both FWA and mobile broadband applications [5]