6月3日，据Wccftech最新报道，台积电2nm制程应用于存储产品的良率已突破90%。分析师指出，由于 台积电正争取与英伟达、苹果、高通、超微和博通等美国主要科技公司的订单，该工厂产能利用率有望 在短期内达到饱和。 该媒体称，苹果仍是台积电亚利桑那工厂的最大客户，并将率先获得该厂生产的芯片。目前台积电正在 美国生产N4芯片，该制程对应5纳米和4纳米芯片。据悉，英伟达的人工智能芯片正在该工厂进行制程 验证，这些芯片预计将于今年年底投产。 业内人士认为，由于美国制造成本上升以及亚利桑那工厂需求旺盛，该厂芯片价格可能上涨高达30%。 Cloud Express的Nobunaga Chai透露，该厂目前月产12英寸晶圆1.5万片，即将扩产至2.4万片，达到工厂 峰值产能。 同时，台积电2nm芯片制程也取得重大突破。据Wccftech，该公司的2nm制程良率已突破90%，不过目 前的高良率适用于存储产品。良率指单个硅晶圆中合格芯片的占比——良率越高，芯片制造商需要承担 的次品生产成本就越低。2nm制程晶圆的订购成本约为3万美元。 根据预计，台积电2nm明年的流片量将达到过去5nm量产次年流片量的4倍。流片指芯片设计的 ...

Core Insights - The semiconductor industry is facing a significant decline in the first silicon tape-out success rate, which has dropped from approximately 30% to a historical low of 14% by 2025, indicating that 8 out of 10 designs may fail [2][4][21] - The complexity of chip design is increasing due to the shift from single-chip to multi-chip components, leading to more iterations and customization, which in turn makes design and verification more time-consuming [1][4][5] - Major companies like AMD and Qualcomm have experienced notable failures in their chip designs, highlighting the challenges posed by complex architectures and advanced manufacturing processes [3][4] Summary by Categories Chip Tape-Out Success Rate - The first tape-out success rate for chips has decreased from 30% to 24% over two years, with projections indicating a further drop to 14% by 2025 [2][4] - The tape-out process is critical for validating chip designs, and any deviation in performance or power consumption can render a chip uncompetitive, necessitating re-tape-out [2][4] Reasons for Decline in Success Rate - Increasing complexity in chip design, particularly with multi-chip components requiring coordination across different manufacturing nodes [4][5] - The rise of customized chips tailored for specific applications, which complicates the design and verification processes [4][5] - A shift in development cycles, where companies are pressured to release products faster, often at the expense of thorough design and verification [4][5] - The rapid advancement of artificial intelligence (AI) is creating higher demands for chip performance, outpacing current semiconductor technology and design capabilities [5][21] Challenges in Chip Yield - Even after successful tape-out, the industry faces challenges with chip yield, which is the ratio of functional chips to total chips produced [10][12] - Major players like TSMC and Samsung are struggling with yield issues, with TSMC achieving around 80% yield for its 5nm process, while Samsung's 3nm yield is significantly lower [13][16][17] - Factors affecting yield include raw material quality, manufacturing environment, and process technology complexities [19][20] Solutions and Future Directions - To improve tape-out success rates, the industry should focus on optimizing designs, utilizing AI for design assistance, and enhancing collaboration across the supply chain [21][22] - For yield improvement, upgrading equipment, selecting high-quality materials, and implementing strict quality control measures throughout the production process are essential [21][22]