Core Insights - The article discusses the transition of 2D semiconductors from a long-term development prospect to a core technology in the semiconductor industry, particularly as the industry moves beyond silicon technology in the mid-2030s [1][4]. Group 1: 2D Semiconductor Technology - 2D semiconductors are gaining attention as they maintain electrical properties even at atomic thickness, making them suitable for future semiconductor applications [1][8]. - Major semiconductor companies and research institutions, including Samsung, TSMC, and Intel, are incorporating 2D semiconductor transistors into their technology roadmaps [1][4]. - The commercialization of 2D semiconductors faces challenges, particularly in gate stack integration technology, which is crucial for device performance and stability [1][4]. Group 2: Gate Stack Engineering - The research team from Seoul National University has developed a comprehensive roadmap for "gate stack engineering," a core technology for 2D transistors [2][4]. - The study categorizes gate stack integration methods into five types: van der Waals dielectrics, vdW-oxidized dielectrics, quasi-vdW dielectrics, vdW-seeded dielectrics, and non-vdW-seeded dielectrics, each evaluated based on various performance metrics [3][4]. - The potential of ferroelectric materials in gate stack technology is highlighted, enabling ultra-low power logic and non-volatile memory applications [4][30]. Group 3: Performance Metrics and Challenges - Key performance indicators for gate stack engineering include subthreshold swing (SS), on-current (I_on), leakage current density (J_leak), threshold voltage (V_T), and power supply voltage (V_dd) [12][22]. - The International Roadmap for Devices and Systems (IRDS) sets ambitious targets for these metrics, such as achieving an equivalent oxide thickness (EOT) below 0.5 nm and a leakage current density below 0.01 A cm^-2 by 2031 [12][24]. - The article emphasizes the need for continuous development in interface engineering and material selection to meet these performance goals and ensure CMOS compatibility [12][29]. Group 4: Future Directions - The integration of ferroelectric materials into gate stacks is seen as a promising direction for developing advanced electronic technologies, including AI semiconductors and ultra-low power mobile chips [4][30]. - The research indicates that overcoming the challenges of high-quality gate stack integration is crucial for the commercialization of 2D transistors, with plans for collaboration between academia and industry to advance device-level integration [4][30].

公众号记得加星标⭐️，第一时间看推送不会错过。 众所周知，大多数当代半导体依赖于硅基互补金属氧化物半导体 (CMOS) 技术。过去几十年 来，这项技术推动了性能和集成密度的提升。然而，随着技术节点进入亚纳米 (nm) 领域，进一 步的微缩越来越受到物理和静电限制。因此，二维 (2D) 半导体作为超越硅的沟道材料，因其即 使在原子厚度下也能保持其电学特性，而受到越来越多的关注。 值得注意的是，包括三星、台积电、英特尔、IMEC在内的全球领先半导体公司和研究机构，已将二 维半导体晶体管作为下一代技术纳入其后硅时代（2030年代中期以后）的技术路线图，并启动了大量 研发项目。因此，二维半导体正从一项长期发展前景转变为全球半导体行业快速崛起的下一代核心技 术。 然而，目前二维半导体商业化面临的最大障碍是栅极堆叠集成技术。作为静电控制沟道导电的核心结 构，栅极堆叠的质量决定了器件的性能和稳定性。然而，将现有的硅晶体管工艺直接应用于二维半导 体，不仅会降低电介质的质量，还会导致界面缺陷、漏电流等问题。开发适合二维界面的新材料和工 艺集成被认为是实现二维半导体商业化的关键任务。 近日，首尔国立大学工程学院宣布，由电气与计算 ...