Workflow
共封装光学器件(CPO)
icon
Search documents
美银2026年半导体展望:AI基建升级关键中点,芯片销售有望首破“万亿”美元大关
美股IPO· 2025-12-18 12:17
的AI工厂将抵消这一影响。半导体设备成AI和回流趋势的"无名英雄",报告预测,2026年晶圆制造设备(WFE)销售额将实现近两位数同比增长。 美银美林最新发布的半导体行业展望显示, 2026年将成为AI基础设施建设的关键中点,全球半导体销售额有望首次突破万亿美元大关,达到1.01万亿 美元,同比增长29%。 美银分析师Vivek Arya等人最新发布的研究报告指出, 尽管AI投资回报和超大规模云服务商现金流面临更严格审视,可能导致股价波动,但更新更快的 大语言模型构建者以及服务企业和政府客户的AI工厂将抵消这一影响。报告预测,2026年晶圆制造设备(WFE)销售额将实现近两位数同比增长。 在先进封装领域,美银注意到这一此前规模较小的市场已增长到足以影响主要半导体设备公司的增长能力。过去一年,先进封装销售额(HBM/逻辑)在 覆盖的半导体设备公司中增长22%,约为整体WFE增长的两倍。 模拟半导体保持谨慎,EDA具备追赶潜力 美银认为,尽管AI投资回报和超大规模云服务商现金流面临更严格审视,可能导致股价波动,但更新更快的大语言模型构建者以及服务企业和政府客户 | CAGR | | | | | | | | | | ...
美银2026年半导体展望:AI基建升级关键中点,芯片销售有望首破“万亿”美元大关
Hua Er Jie Jian Wen· 2025-12-18 08:00
美银美林最新发布的半导体行业展望显示,2026年将成为AI基础设施建设的关键中点,全球半导体销售额有望首次突破万亿美元大关,达到1.01 万亿美元,同比增长29%。 | 2020 | Revenue (Smn) | 2019 | | 2021 | 2022 | 2023 | 2024 | 2025E | 2026E | 2027E | 2028E | CAGR 25-28 | CAGR '20-25 | CAGR '15-25 | | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | | $418 | Total Semis | | $451 | $572 | ਟੇਟਰੇਖ | $528 | 2633 | $783 | $1,010 | $1,154 | $1,257 | 17.1% | 11.7% | 8.9% | | (10.8%) | YoY% | | 7.7% | 27.0% | 3.8% | (11.0%) | 19.7% | 23.7% | 29.0% | 14.3% ...
三星大举杀入硅光赛道
半导体行业观察· 2025-12-03 00:44
Core Viewpoint - Samsung is heavily investing in silicon photonics technology to disrupt the AI chip foundry landscape and challenge TSMC by enhancing data transmission speeds using light [1][2][3]. Group 1: Technology Overview - Silicon photonics is seen as a disruptive technology for the future AI semiconductor market, utilizing light for information transmission, which offers advantages such as higher speed, lower heat generation, and reduced energy consumption [1][2]. - The technology combines silicon, a primary semiconductor material, with photonics, allowing for faster and more efficient data transmission by using light instead of electrical signals [3][4]. - The capacity for data transmission is expected to increase from gigabytes (GB) to terabytes (TB), with speed improvements exceeding 1000 times [3]. Group 2: Market Dynamics - Major semiconductor companies like NVIDIA, AMD, and Intel are shifting towards silicon photonics to meet the growing demand for rapid data processing in AI applications [2][3]. - The silicon photonics market is projected to grow to $10.3 billion (approximately 15 trillion KRW) by 2030, indicating significant market potential [2]. - TSMC is currently the leader in the Co-Packaged Optics (CPO) market, with NVIDIA actively developing silicon photonics technology [6][7]. Group 3: Samsung's Strategy - Samsung has identified silicon photonics as a key technology to attract more large foundry customers and to compete effectively against TSMC in advanced packaging markets [7]. - The company is expanding its global R&D network, particularly in Singapore, to enhance its capabilities in silicon photonics [6][7]. - Samsung plans to commercialize CPO technology by 2027, with competition against TSMC expected to intensify from that point onward [7].
处理器架构,走向尽头?
半导体芯闻· 2025-07-17 10:32
Core Insights - The article emphasizes the shift in processor design focus from solely performance to also include power efficiency, as performance improvements that lead to disproportionate power increases may no longer be acceptable [1][2] - Current architectures are facing challenges in achieving further performance and power efficiency improvements, necessitating a reevaluation of microarchitecture designs [1][3] Group 1: Power Efficiency and Architecture - Processor designers are re-evaluating microarchitectures to control power consumption, with many efficiency improvements still possible through better design of existing architectures [1][2] - Advancements in process technology, such as moving to smaller nodes like 12nm, continue to be a primary method for reducing power consumption [1][2] - 3D-IC technology offers a new power efficiency point, providing lower power and higher speed compared to traditional PCB connections [2][3] Group 2: Implementation Challenges - Asynchronous design presents challenges, as it can lead to unpredictable performance and increased complexity, which may negate potential power savings [3][4] - Techniques like data and clock gating can help reduce power consumption, but they require careful analysis to identify major contributors to power usage [3][4] - The article notes that the most significant power savings opportunities lie at the architecture level rather than the RTL (Register Transfer Level) implementation [3][4] Group 3: AI and Performance Trade-offs - The rise of AI computing has pushed design teams to address the memory wall, balancing execution power and data movement power [5][6] - Architectural features such as speculative execution, out-of-order execution, and limited parallelism are highlighted as complex changes made to improve performance [5][6] - The article discusses the trade-offs between the complexity of features like branch prediction and their impact on area and power consumption [9][10] Group 4: Parallelism and Programming Challenges - Parallelism is identified as a key method for improving performance, but current processors have limited parallelism capabilities [10][11] - The article highlights the challenges of explicit parallel programming, which can deter software developers from utilizing multi-core processors effectively [13][14] - The potential for accelerators to offload tasks from CPUs is discussed, emphasizing the need for efficient design to improve overall system performance [15][16] Group 5: Custom Accelerators and Future Directions - Custom accelerators, particularly NPUs (Neural Processing Units), are gaining attention for their ability to optimize power and performance for specific AI workloads [17][18] - The article suggests that creating application-specific NPUs can significantly enhance efficiency, with reported improvements in TOPS/W and utilization [18][19] - The industry may face a risk of creative stagnation, necessitating new architectural concepts to overcome existing limitations [19]
初创公司,创新光互连
半导体行业观察· 2025-04-27 01:26
来源:内容 编译自 IEEE ,谢谢。 如果将过多的铜线捆扎在一起,最终会耗尽空间——前提是它们不会先熔合在一起。人工智能数据 中心在GPU和内存之间传输数据的电子互连方面也面临着类似的限制。为了满足人工智能的海量 数据需求,业界正在转向更大尺寸、更多处理器的芯片,这意味着在机架内实现更密集、更长距离 的连接。初创公司正在展示 GPU 如何摆脱铜互连,用光纤链路取而代之。 光纤链路对数据中心来说并不陌生。它们使用可插拔收发器在机架之间传输数据,将电信号转换为 光信号。为了提高能源效率,"将光学元件集成到芯片封装中一直是一个梦想,"加州大学圣巴巴拉 分校电气工程教授克林特·肖( Clint Schow)表示。这就是共封装光学器件(CPO),科技巨头们正 在全力支持它。英伟达 (Nvidia) 最近宣布量产一款网络交换机,该交换机使用嵌入在与交换机同 一基板上的光子调制器。"这震惊了整个行业,"加州桑尼维尔初创公司Avicena的首席执行官巴迪 亚·佩泽什基 (Bardia Pezeshki) 表示。 哥伦比亚大学电气工程教授、Xscape Photonics联合创始人Keren Bergman解释说, Nvid ...