Core Viewpoint - The article discusses the advancements in semiconductor technology, particularly the breakthroughs achieved by imec in wafer-to-wafer hybrid bonding and back interconnects, paving the way for CMOS 2.0 technology set to launch in 2024 [1]. Group 1: CMOS 2.0 Technology Core - CMOS 2.0 technology focuses on advanced 3D interconnects and back power delivery networks (BSPDN), enabling high-density connections on both sides of the wafer [2]. - Key milestones presented at the 2025 VLSI symposium include wafer-to-wafer hybrid bonding with a spacing of 250 nanometers (nm) and a back spacing of 120 nm for through-die vias (TDV), addressing performance bottlenecks in AI and mobile applications [2]. Group 2: Wafer-to-Wafer Hybrid Bonding - Wafer-to-wafer hybrid bonding allows for sub-micron spacing, facilitating high bandwidth and low power signal transmission [3]. - The optimized process includes aligning and bonding two processed wafers at room temperature, achieving reliable connections with a spacing of 400 nm using silicon carbon nitride (SiCN) [3]. - imec has reduced bonding spacing to 300 nm with 95% of chip alignment errors under 25 nm, showcasing the feasibility of 250 nm spacing bonding under a hexagonal pad grid architecture [3]. Group 3: Back Interconnect Technology - Back interconnect technology complements front bonding by enabling "front-back" connections through nano-scale silicon vias (nTSV) or direct contact [4]. - This technology allows seamless integration of metal layers on both sides of the wafer, reducing voltage drop and alleviating signal routing congestion in the front-end [4]. - imec demonstrated a back dielectric via (TDV) with a bottom diameter of 20 nm and a spacing of 120 nm, balancing the need for fine spacing connections on both sides of the wafer [4]. Group 4: Advantages of Back Power Delivery Network (BSPDN) - BSPDN enhances CMOS 2.0 performance by relocating power distribution to the back of the wafer, accommodating wider and lower-resistance interconnects [6]. - Research indicates that BSPDN improves power, performance, area, and cost (PPAC) metrics for "always-on" designs and is particularly beneficial for "switch domain" architectures in mobile SoCs [6]. - In 2 nm mobile processor designs, BSPDN reduced voltage drop by 122 millivolts (mV), leading to a 22% area savings while enhancing performance and energy efficiency [6]. Group 5: Technology Implementation and Future Outlook - Supported by pilot lines in nano integrated circuits (NanoIC) and EU funding, these breakthroughs are transitioning CMOS 2.0 from concept to practical application [7]. - The future collaboration with equipment suppliers will be crucial as bonding spacing shrinks below 200 nm to address alignment challenges [7]. - High-density front and back interconnect technologies are expected to usher in a new era of computing innovation, meeting diverse application demands for performance, power, and integration [7].

Core Viewpoint - The article discusses the introduction of CMOS 2.0 by imec in 2024, which aims to address the increasing computational demands driven by diverse applications through a new paradigm of system-on-chip (SoC) design and advanced 3D interconnect technology [2][4][32]. Group 1: CMOS 2.0 Overview - CMOS 2.0 introduces a structured approach to SoC design, dividing it into functional layers optimized with the most suitable technology options based on functional constraints [2]. - The method emphasizes internal heterogeneity within the SoC, allowing for the separation of logic parts into high-drive logic layers and high-density logic layers, each tailored for specific performance and power efficiency [2][4]. Group 2: Key Technologies - A significant feature of CMOS 2.0 is the Backside Power Delivery Network (BSPDN), which powers active devices from the wafer's back, enabling high-density backend processing without voltage drop limitations [4][26]. - The implementation of advanced 3D interconnects and backside technologies is crucial for realizing the CMOS 2.0 vision, with innovations such as wafer-to-wafer hybrid bonding providing sub-micron interconnect spacing [5][10]. Group 3: Performance and Efficiency - The BSPDN concept, first proposed by imec in 2019, has shown potential in enhancing power-performance-area-cost (PPAC) advantages, particularly in high-density and high-drive logic applications [26][27]. - In a comparative study, the use of BSPDN in switch domain designs demonstrated a significant reduction in IR drop by 122mV and a 22% decrease in core area compared to traditional front-end power delivery networks [31]. Group 4: Future Directions - The roadmap for wafer-to-wafer hybrid bonding aims to achieve 200nm interconnect spacing, necessitating advancements in bonding processes and equipment to meet the precision required for high-density interconnects [14][15]. - The integration of nanoscale through-silicon vias (nTSV) is expected to facilitate seamless front-to-back connections, enhancing the overall architecture of CMOS 2.0 [21][24].

Core Viewpoint - The semiconductor industry is transitioning from traditional scaling methods to a new paradigm called CMOS 2.0, which focuses on 3D integration and vertical stacking of components to overcome the limitations of 2D scaling and maintain performance improvements [2][3][34]. Group 1: CMOS 2.0 Overview - CMOS 2.0 aims to break the limitations of single-chip designs by manufacturing each layer independently and optimizing them for their specific functions before stacking them into a unified component [5][10]. - The approach combines four main concepts: backside power delivery, fine-pitch hybrid bonding, complementary FETs (CFET), and a dual-sided process [6][8][9]. Group 2: Technical Pillars of CMOS 2.0 - Backside power delivery moves power rails to the wafer's backside, reducing voltage drop and freeing up routing resources [12]. - Fine-pitch hybrid bonding connects stacked layers using dense copper-to-copper contacts, allowing for high bandwidth and low latency interconnects [12]. - CFET technology vertically stacks n-type and p-type transistors, reducing standard cell height by 30% to 40% and improving density without shortening gate lengths [13]. - The dual-sided process allows for device and contact construction on both sides of the wafer, creating new wiring and integration options [12]. Group 3: Design Rule Changes - CMOS 2.0 fundamentally alters how designers think about system-on-chip (SoC) partitioning, wiring, and verification, requiring early decisions on module placement and current flow [16]. - The design process must adapt to a three-dimensional approach, necessitating new tools for modeling and managing power delivery and signal integrity across multiple layers [17]. Group 4: Manufacturing Challenges - The transition to CMOS 2.0 faces significant manufacturing challenges, particularly in achieving sub-micron hybrid bonding and managing wafer thinning and backside processing [19][20]. - The complexity of integrating multiple technologies into a single process flow poses risks to yield management and process control [19]. Group 5: Economic Considerations - CMOS 2.0 presents potential reliability and cost risks, as any defect in one layer can compromise the entire stack, necessitating rigorous online testing and monitoring [24]. - The economic viability of 3D wafer stacking may vary across markets, with high-performance computing being more likely to absorb the associated costs compared to other sectors [25]. Group 6: Competitive Alternatives - CMOS 2.0 is not the only strategy for scaling; alternatives like 2.5D integration using chiplets and monolithic CFET scaling are also being explored, each with its own advantages and challenges [26][28]. - The choice among these strategies will depend on product requirements, economic constraints, and the readiness of the ecosystem [30]. Group 7: Future Outlook - The success of CMOS 2.0 as a standard platform hinges on overcoming its technical, economic, and logistical challenges, with a focus on achieving reliable, void-free interconnects and mature EDA processes [32][33]. - High-performance computing, AI accelerators, and premium mobile devices are expected to be the initial applications for CMOS 2.0 technology, with broader market adoption possible as yield and process stability improve [34].