公众号记得加星标⭐️，第一时间看推送不会错过。 来源 ：内容 编译自 imec 。 2024年，imec推出了CMOS 2.0作为新的扩展范式，以应对应用多样化带来的日益增长的计算需求。 在CMOS 2.0中，片上系统（SoC）在系统技术协同优化（STCO）的指导下被划分为不同的功能层 （或层级）。每个功能层都采用与功能约束最匹配的技术选项构建。 先进的3D互连技术重新连接了SoC的异构层。这让人想起一项已经应用于商用计算产品的演进：想象 一下在处理器上3D堆叠SRAM芯片。但CMOS 2.0方法的标志是，异构性被引入SoC内部。根据应用 需求，CMOS 2.0甚至设想将SoC的逻辑部分拆分为高驱动逻辑层（针对带宽和性能进行了优化）和 高密度逻辑层（针对逻辑密度和性能功耗比进行了优化）。高密度层可以采用最先进的技术制造，包 括规模最大的晶体管架构。 图 1 ： CMOS 2.0 时代 SoC 可能分区的示例。 另一个关键特性是背面供电网络 (BSPDN)：部分有源器件由晶圆背面供电，而非传统的正面供电方 案。这样，在晶圆层正面实现极高的后端制程 (BEOL) 间距图案化成为可能，且不受电源电压降的限 制。 基 ...

Core Viewpoint - The semiconductor industry is transitioning from traditional scaling methods to a new paradigm called CMOS 2.0, which focuses on 3D integration and vertical stacking of components to overcome the limitations of 2D scaling and maintain performance improvements [2][3][34]. Group 1: CMOS 2.0 Overview - CMOS 2.0 aims to break the limitations of single-chip designs by manufacturing each layer independently and optimizing them for their specific functions before stacking them into a unified component [5][10]. - The approach combines four main concepts: backside power delivery, fine-pitch hybrid bonding, complementary FETs (CFET), and a dual-sided process [6][8][9]. Group 2: Technical Pillars of CMOS 2.0 - Backside power delivery moves power rails to the wafer's backside, reducing voltage drop and freeing up routing resources [12]. - Fine-pitch hybrid bonding connects stacked layers using dense copper-to-copper contacts, allowing for high bandwidth and low latency interconnects [12]. - CFET technology vertically stacks n-type and p-type transistors, reducing standard cell height by 30% to 40% and improving density without shortening gate lengths [13]. - The dual-sided process allows for device and contact construction on both sides of the wafer, creating new wiring and integration options [12]. Group 3: Design Rule Changes - CMOS 2.0 fundamentally alters how designers think about system-on-chip (SoC) partitioning, wiring, and verification, requiring early decisions on module placement and current flow [16]. - The design process must adapt to a three-dimensional approach, necessitating new tools for modeling and managing power delivery and signal integrity across multiple layers [17]. Group 4: Manufacturing Challenges - The transition to CMOS 2.0 faces significant manufacturing challenges, particularly in achieving sub-micron hybrid bonding and managing wafer thinning and backside processing [19][20]. - The complexity of integrating multiple technologies into a single process flow poses risks to yield management and process control [19]. Group 5: Economic Considerations - CMOS 2.0 presents potential reliability and cost risks, as any defect in one layer can compromise the entire stack, necessitating rigorous online testing and monitoring [24]. - The economic viability of 3D wafer stacking may vary across markets, with high-performance computing being more likely to absorb the associated costs compared to other sectors [25]. Group 6: Competitive Alternatives - CMOS 2.0 is not the only strategy for scaling; alternatives like 2.5D integration using chiplets and monolithic CFET scaling are also being explored, each with its own advantages and challenges [26][28]. - The choice among these strategies will depend on product requirements, economic constraints, and the readiness of the ecosystem [30]. Group 7: Future Outlook - The success of CMOS 2.0 as a standard platform hinges on overcoming its technical, economic, and logistical challenges, with a focus on achieving reliable, void-free interconnects and mature EDA processes [32][33]. - High-performance computing, AI accelerators, and premium mobile devices are expected to be the initial applications for CMOS 2.0 technology, with broader market adoption possible as yield and process stability improve [34].