Summary of NVIDIA Co-Packaged Optics (CPO) Conference Call Company and Industry Overview - **Company**: NVIDIA - **Industry**: Technology, specifically focusing on AI server architecture and optical networking solutions Key Points and Arguments 1. **Introduction of CPO**: NVIDIA's Co-Packaged Optics (CPO) was first introduced two years ago, with a formal announcement of its product portfolio at the GTC conference in March last year. However, there have been no significant developments in the CPO field until recent discussions about its application in the upcoming Rubin Ultra racks [4][5][6] 2. **CPO Vision**: NVIDIA aims to create AI server racks with Optical Input/Output (OIO) all-optical interconnects, co-packaging GPU and switch chips with optical engines to eliminate intermediate optical-electrical conversion steps [7][9] 3. **Gradual Implementation**: The implementation of the OIO design will be gradual, starting with CPO switches for Scale-Out networks, followed by adoption in NVSwitch trays for Scale-Up networks, and finally on GPGPU chips [9][10] 4. **Rubin Ultra Rack Configuration**: The CPO solution for Rubin Ultra racks will feature an NVL72 x 2 configuration, allowing for 144 GPGPU cards interconnected via CPO and optical fiber [13][14] 5. **Switching Capacity**: Each NVSwitch chip in the CPO solution will have a switching capacity of 14.4T, with a total capacity of 86.4T per NVSwitch tray. The entire Rubin Ultra rack will require 144 CPO NVSwitch chips and 648 optical engines [15][16][17] 6. **Bandwidth Upgrades**: The per-GPU card bandwidth will be upgraded to 28.8 Tb/s, leading to a total bandwidth of 4147.2T for the entire Rubin Ultra racks [17] 7. **CPO Adoption in Scale-Out Network**: The backend Scale-Out network will also utilize CPO, with each CX10 NIC co-packaged with a 3.2T optical engine [19][20] 8. **Serviceability Challenges**: A major criticism of CPO is its serviceability; if an optical engine fails, the entire switch chip must be replaced. NVIDIA addresses this with a detachable design in its Quantum X800 CPO switch [27][29] 9. **Supplier Insights**: The suppliers for the CPO solution remain largely unchanged from previous discussions, with additional companies like LOTES and Teradyne identified as beneficiaries of the CPO architecture [24][26][36] 10. **Financial Projections for Suppliers**: - LOTES could see additional revenues of $82.5 million in 2027 and $247.5 million in 2028 from the CPO version of Rubin Ultra racks, accounting for 8% and 25% of its total revenue, respectively [34][35] - Teradyne could generate $1.1 billion in 2027 and $1.8 billion in 2028 from CPO testing systems, representing 35% and 57% of its total revenue, respectively [51][52] 11. **Emerging Japanese Players**: Mipox and Seikoh Giken are identified as niche players in the CPO market, providing materials and equipment for optical fiber ferrule polishing, with both holding approximately 60% of the global market share [61][62] 12. **Market Growth**: The transition to optical fiber connections in NVIDIA's CPO-version Rubin Ultra racks is expected to create a new market for suppliers of high-speed fiber ferrules and related equipment [70][71] Additional Important Content - **Technical Challenges**: The heterogeneous architecture of NVIDIA's CPO optical engines presents significant challenges for testing equipment, which FiconTEC addresses with its unique double-sided wafer testing solutions [42][44] - **Market Dynamics**: The rapid growth in optical fiber usage in data centers is driving demand for polishing machines and inspection equipment, indicating a robust market outlook for companies involved in this segment [63][65]

Core Viewpoint - The event "Networking for AI" highlighted the progress of the domestic AI computing power industry chain and emphasized the importance of collaboration among industry players to achieve a closed-loop ecosystem for AI computing power in China [1][3][6]. Group 1: Event Overview - The "Networking for AI" ecosystem salon was successfully held in Shanghai, focusing on the theme of achieving a closed-loop in the domestic AI computing power industry chain [1]. - Key industry players and technical experts from companies like China Mobile, Tencent Cloud, and others participated, showcasing advancements from computing chips to algorithm models and computing services [1][3]. Group 2: Industry Insights - The East China Branch of the China Academy of Information and Communications Technology emphasized the need for technological innovation, improved computing power scheduling systems, and deeper application integration to enhance the quality of the AI computing power industry in Shanghai [3]. - The shift from hardware procurement to ecosystem adaptation and co-construction in intelligent computing centers is crucial for overcoming domestic computing power bottlenecks [4][6]. Group 3: Technological Developments - The article discusses the significance of interconnect technology in AI infrastructure, highlighting its role in enhancing model performance and reducing costs [6][7]. - NVIDIA's advancements in interconnect technology, such as NVLink, are noted as strategic pillars for GPU communication, with high bandwidth capabilities [7][10]. Group 4: Collaborative Initiatives - The OISA (Open Intelligent Sensing Architecture) initiative aims to break traditional bandwidth and latency bottlenecks, facilitating large-scale deployment of AI computing clusters [14][15]. - Major companies like China Mobile and Xinhua San are collaborating to promote the integration of computing power and interconnect technology, with the OISA 2.0 protocol supporting up to 1024 AI chips and achieving TB/s bandwidth [14][15]. Group 5: Future Outlook - The demand for AI computing power is shifting from individual intelligence to collective intelligence, making interconnect technology increasingly vital for enhancing computing density and performance [18]. - The article concludes that the ability to effectively interconnect domestic computing power will be a key factor in winning the AI infrastructure competition in the coming years [18].