如果您希望可以时常见面，欢迎标星收藏哦~ IEEE IEDM 会议由 IEEE 电子器件学会主办，是全球规模最大、最具影响力的论坛，旨在展 示晶体管及相关微纳电子器件领域的突破性进展。 在第 70 届 IEEE IEDM 会议上，他们以"塑造未来的半导体技术"分享了芯片的未来技术。我 们摘录如下，以飨读者。 先进的逻辑技术 基于纳米片的晶体管以及由纳米片构建的3D互补场效应晶体管 (CFET) 是延续摩尔定律微缩的关 键，因为现有的FinFET架构正在达到其性能极限。纳米片是一种环栅 (GAA) 晶体管架构，其中 硅堆叠的沟道完全被栅极包围。它们比FinFET具有更好的静电控制、相对较高的驱动电流和可变 的宽度。而CFET是高度集成的3D设计，其中n-FET和p-FET纳米片相互堆叠。这些堆叠器件可以 单片构建（在同一晶圆上），也可以顺序构建（在单独的晶圆上构建，然后进行转移和集成）。 堆叠器件本质上使晶体管密度翻倍，而无需增加器件尺寸，从而实现更强大的功能，并提高功率效 率和性能。在 IEDM 2024 上，多篇论文推动了以下领域的最前沿研究： 一、台积电全新业界领先的 2 纳米 CMOS 逻辑平台 台积电 ...

Core Insights - The IEEE IEDM conference showcased groundbreaking advancements in semiconductor technology, focusing on the future of chips and their applications in AI, mobile, and high-performance computing [1]. Advanced Logic Technologies - The introduction of nanosheet transistors and 3D complementary field-effect transistors (CFET) is crucial for continuing the miniaturization trend of Moore's Law, as current FinFET architectures reach performance limits [3]. - TSMC's upcoming 2nm CMOS logic platform (N2) is set to enhance chip density by over 1.15 times, with a 15% speed increase and a 30% reduction in power consumption compared to the existing 3nm CMOS platform (N3) [4]. - The N2 platform utilizes GAA nanosheet transistors and features the highest density SRAM macro to date, with plans for risk production in 2025 and mass production in late 2025 [4]. - Intel's RibbonFET technology demonstrates the ability to scale down gate lengths to 6nm while maintaining electron mobility, with a focus on achieving low threshold voltages [8][9]. - A fully functional advanced CFET inverter with a gate length of 48nm was demonstrated, marking a significant milestone in CFET technology for future logic applications [14]. Emerging Materials and Devices - High-density aligned carbon nanotube (A-CNT) arrays have shown potential in extending Moore's Law, with a record-setting 100nm gate length MOSFET achieving a saturation current of 2.45mA/μm [22][23]. - Researchers have achieved a record subthreshold slope in WSe2 PMOS devices, highlighting the potential of two-dimensional materials in next-generation electronics [31]. DRAM Innovations - A new 4F2 DRAM design using GAA IGZO vertical channel transistors has been developed, demonstrating significant potential for high-density, low-power applications [33]. - Research on IGZO TFT threshold voltage instability has identified solutions to enhance reliability in future memory technologies [39]. Memory Computing Advances - A 3D integrated chip based on metal-oxide CFET has been developed, significantly reducing area, delay, and energy consumption compared to 2D CIM circuits [48]. - 3D FeNAND arrays have shown a 4,000-fold increase in CIM density, with a computation efficiency 1,000 times higher than 2D arrays [50]. High-Frequency and Power Devices - Intel's GaN MOSHEMT transistors, built on a 300mm GaN-on-TRSOI substrate, exhibit excellent RF performance, crucial for advancing 6G wireless communication [54][56]. - A Ga2O3 JFET has been developed to operate at 250°C, showcasing its potential for high-voltage applications in power electronics [58]. Sensor and Imaging Developments - A multi-modal sensor capable of measuring pressure, gas, and temperature has been developed, achieving high accuracy and sensitivity [65]. - Sony researchers have created a single-chip solution for simultaneous RGB imaging and distance measurement, enhancing mobile device capabilities [68]. Diverse Research Themes - Interest in selector-only memory (SOM) technology is growing, with research focusing on optimizing materials for better performance and reliability [78][79]. - AI-driven simulations are being utilized to model thermal behavior in electronic devices, addressing challenges in temperature management [81][82].