Core Viewpoint - AMD has confirmed the acquisition of employees from Untether AI, a developer of AI inference chips, which are claimed to be faster and more energy-efficient than competitors' products in edge environments and enterprise data centers [1][2]. Group 1: Acquisition Details - AMD has reached a strategic agreement to acquire a talented team of AI hardware and software engineers from Untether AI, enhancing its AI compiler and kernel development capabilities [1]. - The financial details of the transaction were not disclosed by AMD [1]. - Untether AI will cease to provide support for its speedAI products and imAIgine software development suite as part of the acquisition [1]. Group 2: Untether AI's Background and Technology - Untether AI, founded in 2018, focuses on AI inference and has raised a total of $152 million, with its latest funding round exceeding $125 million [2][6]. - The company introduced its second-generation memory architecture, speedAI240, designed to improve energy efficiency and density, and is capable of scaling for various device sizes [2][5]. - The new "Boqueria" chip, built on TSMC's 7nm process, offers 2 petaflops of FP8 performance and 238 MB of SRAM, significantly enhancing performance and energy efficiency compared to its predecessor [5][10]. Group 3: Technical Innovations - Untether AI's memory computing architecture aims to address key challenges in AI inference, providing unmatched energy efficiency and scalability for neural networks [5][6]. - The architecture allows for a variety of data types, enabling organizations to balance accuracy and throughput according to their specific application needs [5][9]. - The speedAI240 device features two RISC-V processors, managing 1,435 cores, and supports external memory through PCI-Express Gen5 interfaces [10][20]. Group 4: Software and Ecosystem Development - AMD has also acquired Brium, a software company, to strengthen its open AI software ecosystem, enhancing capabilities in compiler technology and AI inference optimization [24][25]. - Brium's expertise will contribute to key projects like OpenAI Triton and WAVE DSL, facilitating faster and more efficient execution of AI models on AMD hardware [25][26]. - The acquisition aligns with AMD's commitment to providing an open, scalable AI software platform, aiming to meet the specific needs of various industries [26][27].

如果您希望可以时常见面，欢迎标星收藏哦~ IEEE IEDM 会议由 IEEE 电子器件学会主办，是全球规模最大、最具影响力的论坛，旨在展 示晶体管及相关微纳电子器件领域的突破性进展。 在第 70 届 IEEE IEDM 会议上，他们以"塑造未来的半导体技术"分享了芯片的未来技术。我 们摘录如下，以飨读者。 先进的逻辑技术 基于纳米片的晶体管以及由纳米片构建的3D互补场效应晶体管 (CFET) 是延续摩尔定律微缩的关 键，因为现有的FinFET架构正在达到其性能极限。纳米片是一种环栅 (GAA) 晶体管架构，其中 硅堆叠的沟道完全被栅极包围。它们比FinFET具有更好的静电控制、相对较高的驱动电流和可变 的宽度。而CFET是高度集成的3D设计，其中n-FET和p-FET纳米片相互堆叠。这些堆叠器件可以 单片构建（在同一晶圆上），也可以顺序构建（在单独的晶圆上构建，然后进行转移和集成）。 堆叠器件本质上使晶体管密度翻倍，而无需增加器件尺寸，从而实现更强大的功能，并提高功率效 率和性能。在 IEDM 2024 上，多篇论文推动了以下领域的最前沿研究： 一、台积电全新业界领先的 2 纳米 CMOS 逻辑平台 台积电 ...

如果您希望可以时常见面，欢迎标星收藏哦~ IEEE IEDM 会议由 IEEE 电子器件学会主办，是全球规模最大、最具影响力的论坛，旨在展 示晶体管及相关微纳电子器件领域的突破性进展。 台积电研究人员发布了全球最先进的逻辑技术。这是该公司即将推出的 2 纳米 CMOS（即 N2） 平台，旨在实现人工智能、移动和高性能计算 (HPC) 应用的节能计算。与目前量产的最先进的逻 辑技术——台积电自主研发的 3 纳米 CMOS（N3）平台（于 2022 年底推出）相比，该平台在芯 片密度增加 1.15 倍以上的情况下，速度提升 15%（功耗降低 30%）。 全新 N2 平台采用 GAA 纳米片晶体管；中/后端线路互连，以及迄今为止密度最高的 SRAM 宏 （约 38Mb/mm²）；以及一个整体的、系统技术协同优化 (STCO) 架构，可提供出色的设计灵活 性。该架构包括可扩展的铜基重分布层和平坦钝化层（用于实现更佳性能、强大的 CPI 和无缝 3D 集成）；以及硅通孔 (TSV)（用于通过 F2F/F2B 堆叠传输电源/信号）。研究人员表示，N2 平台 目前处于风险生产阶段，计划于 2025 年下半年实现量产。 N2 ...