Core Viewpoint - SRAM is a critical component in all computing systems, but it has failed to keep pace with the expansion of logic circuits, leading to increasingly challenging issues, particularly over the past five years [1][4]. Group 1: Memory Wall and SRAM Challenges - The concept of the "memory wall" was identified as a key bottleneck for future processing capabilities, with memory capacity and performance becoming critical issues [1][4]. - SRAM's capacity and performance improvements have stagnated, resulting in a higher proportion of chip area being occupied by SRAM as process nodes shrink, leading to increased reliance on slower external memory [4][8]. - The performance of processors is often limited by memory and memory bandwidth rather than computational power, with many processors operating at only 20% utilization [7][9]. Group 2: Technological Limitations - Traditional 6T SRAM cells have reached physical and process deviation limits, hindering further miniaturization and performance improvements [8]. - As process nodes shrink, factors such as electrostatic control and random fluctuations become significant constraints, limiting SRAM density improvements to less than 15% at advanced 2nm nodes, compared to 50%-100% improvements seen in earlier nodes [8][9]. - The gap between memory density growth and logic density growth has been widening since the 1980s, with current computer performance improvements not matching memory bandwidth enhancements [9]. Group 3: Software Implications - The reliance on large local SRAM and multi-layer caches in processor architectures is increasingly challenged, as SRAM occupies a larger proportion of chip area and cost [11]. - Software must adapt to a more complex memory hierarchy, with locality, partitioning, and predictability becoming critical for system-level performance [11][12]. - AI models are particularly affected, as memory bandwidth and on-chip cache become performance bottlenecks, necessitating optimizations in data locality and memory-aware scheduling [12]. Group 4: Alternative Solutions - The industry is exploring 3D stacking technologies and chiplet designs to address SRAM limitations, allowing for higher bandwidth and lower power consumption [13][17]. - Emerging memory technologies like MRAM and ReRAM are gaining traction, offering scalability and cost advantages, but they are not expected to fully replace SRAM [15][16]. - The concept of memory computing or near-memory computing is evolving, indicating a shift in traditional models as SRAM scalability issues become more pronounced [15]. Conclusion - The memory bottleneck is becoming increasingly evident, with little sign of change in the short term. The expansion of SRAM is unlikely to return to previous levels, necessitating the search for alternative solutions and more efficient utilization of existing memory [18].

Core Insights - The demand for low-power memory close to computing logic is driven by artificial intelligence workloads, leading to new memory designs and material explorations across various applications [1][11] - DRAM remains the preferred technology for most applications despite challenges in miniaturization and increasing demand from AI data centers, resulting in a memory shortage in the industry [1][11] Group 1: DRAM and Memory Technologies - The miniaturization of DRAM faces challenges, with designers looking to vertical structures to increase density while avoiding high lithography costs [1] - Low-leakage transistors are being explored to reduce refresh power in large storage arrays, with materials like IGZO showing promise due to their acceptable carrier mobility and low leakage [1][2] - Research from Samsung indicates that zinc migration during IGZO annealing can lead to uncoordinated indium sites, affecting performance, but optimizing electrode materials can mitigate interface migration and oxygen loss [2] Group 2: Innovations in Oxide Semiconductors - Researchers from Changxin Storage Technology successfully created functional IGZO devices by optimizing deposition processes and reducing hydrogen content, achieving a drive current of 60.9 μA/μm [3] - Kioxia demonstrated a 3D DRAM oxide channel replacement process that helps reduce thermal degradation, achieving over 30 μA per cell in prototype storage units [5] - A hybrid design using oxide semiconductors and silicon in a 256×256 array improved density by 3.6 times and reduced energy consumption by 15% compared to high-density SRAM [6] Group 3: Advanced Memory Architectures - A fully self-aligned design by Georgia Tech improved performance by 10 times and reduced energy-delay-area product by 75% to 80% compared to traditional SRAM cells [8] - Researchers are exploring the integration of transistor-based memory into backend processes, balancing speed and maturity of silicon technology with simpler but lower-performing alternatives [8] - Non-volatile memory designs using ferroelectric layers and IGZO as channel materials have shown promising durability and performance, with a wide storage window of 1.6 V [9]

Core Insights - NeuroBlade's core engineering team will join AWS Annapurna Labs, marking the effective end of the company's independent operations [1][2] - The company aims to become "the Nvidia of data analytics," focusing on accelerating SQL processing through specialized hardware [3][7] Company Overview - NeuroBlade was founded in 2018 by Elad Sity and Eliad Hillel, both former employees of SolarEdge, and has raised $110 million in funding from investors including Intel Capital and Corner Ventures [1] - The company has developed a novel data analytics architecture that integrates computation directly into memory to eliminate bottlenecks in data processing [2][3] Strategic Developments - The acquisition of NeuroBlade's engineering team by AWS is seen as a significant milestone, with expectations for exponential growth in impact and innovation [2] - NeuroBlade has completed internal organizational adjustments prior to the AWS deal, focusing on transformative next steps [2] Technology and Product Focus - NeuroBlade's technology allows for a 100-fold increase in processing speed for SQL workloads on x86 servers, significantly reducing costs and improving CPU core utilization [3] - The company has developed a dedicated semiconductor chip for accelerating SQL instruction processing, which integrates seamlessly into existing server architectures [3][6] Market Engagement - NeuroBlade is actively engaging with major hyperscale data center operators and has signed contracts for thousands of SPU cards [4] - A partnership with Dell has been established to distribute SPU card products in PowerEdge servers, indicating strong market interest [5] Future Directions - The company is exploring the deployment of SPU cards in storage arrays but is currently prioritizing sales to hyperscale data centers, which promise higher returns [6] - NeuroBlade's technology is expected to enable significant cost savings for large-scale customers, potentially saving millions annually [6]

Core Viewpoint - The article discusses the significant demand for memory bandwidth and capacity in AI inference workloads, highlighting d-Matrix's innovative 3D Stacked In-Memory Compute (3DIMC) architecture as a solution to address these challenges [2][5][8]. Group 1: Company Overview - d-Matrix was founded in 2019 by Sid Sheth and Sudeep Bhoja, both former executives at Inphi Corp, which was acquired by Marvell for $10 billion in 2020 [2]. - The company aims to develop memory compute chip-level technology that offers greater bandwidth than traditional DRAM at a lower cost compared to High Bandwidth Memory (HBM) [2]. Group 2: Technology and Innovation - The 3DIMC architecture integrates 3D stacked memory with computing capabilities, significantly reducing latency and enhancing bandwidth while improving efficiency [3][8]. - d-Matrix's technology utilizes LPDDR5 memory and connects Digital In-Memory Compute (DIMC) hardware to memory via an intermediary layer, optimizing for matrix-vector multiplication, a key operation in transformer-based models [3][5]. Group 3: Performance Expectations - d-Matrix anticipates that 3DIMC will enhance memory bandwidth and capacity for AI inference workloads by several orders of magnitude, enabling efficient and cost-effective large-scale operations as new models and applications emerge [5][9]. - The next-generation architecture, Raptor, is expected to incorporate 3DIMC, aiming for a tenfold increase in memory bandwidth and energy efficiency compared to HBM4 when running AI inference workloads [5][9]. Group 4: Market Trends and Predictions - The article notes a significant shift from AI training to AI inference, with d-Matrix positioned to meet the growing demand for faster and larger memory solutions driven by large language models (LLMs) [6][7]. - Sheth predicts that the reliance on transformer models will dominate AI computing for the next 5 to 10 years, leading to a surge in AI inference workloads [6].

Core Viewpoint - AMD has confirmed the acquisition of employees from Untether AI, a developer of AI inference chips, which are claimed to be faster and more energy-efficient than competitors' products in edge environments and enterprise data centers [1][2]. Group 1: Acquisition Details - AMD has reached a strategic agreement to acquire a talented team of AI hardware and software engineers from Untether AI, enhancing its AI compiler and kernel development capabilities [1]. - The financial details of the transaction were not disclosed by AMD [1]. - Untether AI will cease to provide support for its speedAI products and imAIgine software development suite as part of the acquisition [1]. Group 2: Untether AI's Background and Technology - Untether AI, founded in 2018, focuses on AI inference and has raised a total of $152 million, with its latest funding round exceeding $125 million [2][6]. - The company introduced its second-generation memory architecture, speedAI240, designed to improve energy efficiency and density, and is capable of scaling for various device sizes [2][5]. - The new "Boqueria" chip, built on TSMC's 7nm process, offers 2 petaflops of FP8 performance and 238 MB of SRAM, significantly enhancing performance and energy efficiency compared to its predecessor [5][10]. Group 3: Technical Innovations - Untether AI's memory computing architecture aims to address key challenges in AI inference, providing unmatched energy efficiency and scalability for neural networks [5][6]. - The architecture allows for a variety of data types, enabling organizations to balance accuracy and throughput according to their specific application needs [5][9]. - The speedAI240 device features two RISC-V processors, managing 1,435 cores, and supports external memory through PCI-Express Gen5 interfaces [10][20]. Group 4: Software and Ecosystem Development - AMD has also acquired Brium, a software company, to strengthen its open AI software ecosystem, enhancing capabilities in compiler technology and AI inference optimization [24][25]. - Brium's expertise will contribute to key projects like OpenAI Triton and WAVE DSL, facilitating faster and more efficient execution of AI models on AMD hardware [25][26]. - The acquisition aligns with AMD's commitment to providing an open, scalable AI software platform, aiming to meet the specific needs of various industries [26][27].

如果您希望可以时常见面，欢迎标星收藏哦~ IEEE IEDM 会议由 IEEE 电子器件学会主办，是全球规模最大、最具影响力的论坛，旨在展 示晶体管及相关微纳电子器件领域的突破性进展。 在第 70 届 IEEE IEDM 会议上，他们以"塑造未来的半导体技术"分享了芯片的未来技术。我 们摘录如下，以飨读者。 先进的逻辑技术 基于纳米片的晶体管以及由纳米片构建的3D互补场效应晶体管 (CFET) 是延续摩尔定律微缩的关 键，因为现有的FinFET架构正在达到其性能极限。纳米片是一种环栅 (GAA) 晶体管架构，其中 硅堆叠的沟道完全被栅极包围。它们比FinFET具有更好的静电控制、相对较高的驱动电流和可变 的宽度。而CFET是高度集成的3D设计，其中n-FET和p-FET纳米片相互堆叠。这些堆叠器件可以 单片构建（在同一晶圆上），也可以顺序构建（在单独的晶圆上构建，然后进行转移和集成）。 堆叠器件本质上使晶体管密度翻倍，而无需增加器件尺寸，从而实现更强大的功能，并提高功率效 率和性能。在 IEDM 2024 上，多篇论文推动了以下领域的最前沿研究： 一、台积电全新业界领先的 2 纳米 CMOS 逻辑平台 台积电 ...

Core Insights - The IEEE IEDM conference showcased groundbreaking advancements in semiconductor technology, focusing on the future of chips and their applications in AI, mobile, and high-performance computing [1]. Advanced Logic Technologies - The introduction of nanosheet transistors and 3D complementary field-effect transistors (CFET) is crucial for continuing the miniaturization trend of Moore's Law, as current FinFET architectures reach performance limits [3]. - TSMC's upcoming 2nm CMOS logic platform (N2) is set to enhance chip density by over 1.15 times, with a 15% speed increase and a 30% reduction in power consumption compared to the existing 3nm CMOS platform (N3) [4]. - The N2 platform utilizes GAA nanosheet transistors and features the highest density SRAM macro to date, with plans for risk production in 2025 and mass production in late 2025 [4]. - Intel's RibbonFET technology demonstrates the ability to scale down gate lengths to 6nm while maintaining electron mobility, with a focus on achieving low threshold voltages [8][9]. - A fully functional advanced CFET inverter with a gate length of 48nm was demonstrated, marking a significant milestone in CFET technology for future logic applications [14]. Emerging Materials and Devices - High-density aligned carbon nanotube (A-CNT) arrays have shown potential in extending Moore's Law, with a record-setting 100nm gate length MOSFET achieving a saturation current of 2.45mA/μm [22][23]. - Researchers have achieved a record subthreshold slope in WSe2 PMOS devices, highlighting the potential of two-dimensional materials in next-generation electronics [31]. DRAM Innovations - A new 4F2 DRAM design using GAA IGZO vertical channel transistors has been developed, demonstrating significant potential for high-density, low-power applications [33]. - Research on IGZO TFT threshold voltage instability has identified solutions to enhance reliability in future memory technologies [39]. Memory Computing Advances - A 3D integrated chip based on metal-oxide CFET has been developed, significantly reducing area, delay, and energy consumption compared to 2D CIM circuits [48]. - 3D FeNAND arrays have shown a 4,000-fold increase in CIM density, with a computation efficiency 1,000 times higher than 2D arrays [50]. High-Frequency and Power Devices - Intel's GaN MOSHEMT transistors, built on a 300mm GaN-on-TRSOI substrate, exhibit excellent RF performance, crucial for advancing 6G wireless communication [54][56]. - A Ga2O3 JFET has been developed to operate at 250°C, showcasing its potential for high-voltage applications in power electronics [58]. Sensor and Imaging Developments - A multi-modal sensor capable of measuring pressure, gas, and temperature has been developed, achieving high accuracy and sensitivity [65]. - Sony researchers have created a single-chip solution for simultaneous RGB imaging and distance measurement, enhancing mobile device capabilities [68]. Diverse Research Themes - Interest in selector-only memory (SOM) technology is growing, with research focusing on optimizing materials for better performance and reliability [78][79]. - AI-driven simulations are being utilized to model thermal behavior in electronic devices, addressing challenges in temperature management [81][82].