Core Viewpoint - Micron Technology presented its latest 3D NAND flash technology, the ninth generation (G9), at the 2025 IEEE International Memory Workshop, highlighting significant advancements in storage density and data transfer speeds while maintaining the same storage capacity per chip as the previous generation [1]. Summary by Sections G9 3D NAND Flash Technology - The G9 3D NAND flash has a storage capacity of 1 Tbit per chip, the same as the G8, but with a 40% increase in storage density of the memory cell array and a 30% increase in chip storage density [1]. - The maximum data transfer speed of G9 has improved by 1.5 times compared to G8 [1]. - The number of word line layers in G9 is 276, only a 19% increase from the 232 layers in G8, indicating that innovations beyond just increasing layer count contributed to the density improvements [1]. Storage Density Improvements - The storage density of Micron's memory cell array increased from 17 Gbit/mm² in G7 to 25 Gbit/mm² in G8, and further to 35 Gbit/mm² in G9 [3]. - Innovations include the removal of virtual pillars, which reduced block height by approximately 14%, and a decrease in the number of page buffers from 16 in G8 to 6 in G9, halving the page buffer's chip area [3]. Future Technology Challenges - The future of 3D NAND flash technology, including G10 and beyond, will face increasing technical challenges, akin to climbing an infinitely long spiral staircase [5]. - The introduction of "Confined SN" technology aims to reduce interference between adjacent cells, resulting in a 10% reduction in programming time and a 50% decrease in coupling capacitance between adjacent cells [9]. Innovations and Solutions - The G9 stack height exceeds 13 μm, with a layer height of 6.5 μm, and a high aspect ratio of over 43 due to the small diameter of storage holes [7]. - To mitigate electrical interference, Micron introduced air gaps in the insulation film and limited the nitrogen film to the gate side of the cell transistors [7][8]. - The transition from charge trapping to ferroelectric polarization is proposed as a solution to reduce the risk of dielectric breakdown, which is critical as the number of layers increases [16]. Cost and Performance Considerations - Micron is exploring wafer bonding technology to optimize the performance of peripheral circuits and memory cell arrays, despite the initial increase in costs associated with wafer bonding [12]. - The cost of wafer bonding is expected to decrease with each new technology generation, potentially becoming more cost-effective than single-chip manufacturing in the future [12][14].

Core Viewpoint - The semiconductor industry is witnessing intense competition among leading foundries like TSMC, Intel, and Samsung in the development of 2nm and 1nm technologies, with TSMC planning to establish a 1nm fab in Taiwan to maintain its market leadership [1][6][7]. Group 1: Advanced Lithography and Technology Partnerships - ASML and Imec have formed a five-year partnership to enhance research capabilities for technologies below 2nm, utilizing ASML's latest lithography tools [3][4]. - Imec will integrate ASML's advanced wafer fabrication equipment, including High-NA EUV tools, into its facilities in Belgium, marking a significant step in semiconductor manufacturing technology [4][5]. - High-NA EUV systems, essential for efficient manufacturing at 2nm nodes, can cost up to $350 million each, posing a barrier for new entrants [4]. Group 2: TSMC's 1nm Development Plans - TSMC is accelerating its 1nm technology development and plans to build a 1nm fab in Tainan, Taiwan, with six production lines dedicated to 1nm and 1.4nm chips [6][7]. - The new fab aims to outpace competitors like Samsung and Intel, with TSMC initially planning to launch 1.4nm technology in 2027 but now targeting 2026 for 1.6nm production [7]. Group 3: EUV Technology Advancements - DNP has successfully developed the first generation of EUV masks required for 2nm and beyond, achieving a resolution that is 20% smaller than that needed for 3nm [8][9]. - The company is collaborating with Imec to advance mask manufacturing technology, focusing on the requirements for 1nm processes [9]. Group 4: Future Roadmaps and Challenges - Imec's roadmap includes the transition from FinFET to GAA (Gate-All-Around) transistors at the 2nm node, with further innovations expected to continue down to atomic channel designs [11][12]. - The industry faces challenges such as rising design costs and the need for increased computational power, particularly for machine learning applications, which are growing at a faster rate than traditional transistor scaling can accommodate [13][14]. - Imec emphasizes the importance of next-generation tools and techniques, such as High-NA EUV lithography, to achieve higher transistor densities and performance [15][16].