如果您希望可以时常见面，欢迎标星收藏哦~ 根据Wccftech 报导，传英伟达极可能成为台积电A16 制程（1.6 纳米）的唯一客户，并已将此 技术锁定于英伟达新一代GPU「Feynman」。 供 应 链 消 息 显 示 ， 英 伟 达 的 Rubin 与 Rubin Ultra 系 列 将 率 先 采 用 3 纳 米 ， 而 再 下 一 代 的 Feynman 则计画直接跨入A16。为配合此时程，台积电高雄P3 厂正加速建置，预计在2027 年 替英伟达启动量产。近期台积电扩充3 纳米产能，也被业界解读为因应英伟达大量拉货、并提 前为A16 布局。 A16 采用纳米片电晶体架构，并搭配SPR 背面供电技术，可释放更多正面布局空间、提升逻辑 密度并降低压降，其背面接面（Backside Contact） 亦能维持传统版图弹性，是业界首创的背 面供电整合方案。相较N2P，A16 在相同电压下速度提升8–10%，相同速度下降低15–20% 功 耗，芯片密度提升至1.10 倍，特别适合AI 与HPC 等高运算密度芯片。 除了台积电外，其他晶圆大厂也正加速布局背面供电技术。三星已在今年的晶圆代工论坛宣 布，将于202 ...

Core Insights - The next significant leap in CPU design is expected to come from backside power delivery technology, which can transform performance, thermal management, and energy efficiency, particularly for enterprise markets and PC enthusiasts [2][3]. Group 1: Backside Power Delivery Technology - Backside power delivery (BSPD) involves relocating the power delivery network (PDN) from the front to the back of the silicon chip, allowing the front to be fully utilized for signal output and transistors [2][3]. - Intel's PowerVia PDN is the first commercial implementation of backside power delivery, initially planned for the 20A process node but now expected to debut with the Panther Lake architecture based on the 18A node in early 2026 [3][4]. Group 2: Performance and Efficiency Improvements - Power delivery is a critical yet often overlooked bottleneck that affects CPU performance limits, as every watt of power must be transmitted without interfering with logic signals [4]. - Intel's tests indicate that moving the power circuit to the chip's bottom can increase clock frequency by 6% and reduce voltage drop by 30% under the same process node and voltage [4]. Group 3: Thermal Management and Future Innovations - The relocation of power circuits to the back enhances thermal contact with integrated heat spreaders, potentially simplifying CPU cooling and reducing voltage spikes during load [4][5]. - Backside power delivery aligns well with future stacking technologies, enabling true logic stacking rather than just additional cache, which could lead to more efficient designs as manufacturing costs rise and silicon capabilities approach their limits [5].

Group 1: Core Insights - The flagship smartphones of 2025 will not feature 2nm chips, with major companies like Apple and Qualcomm opting for 3nm technology instead [1][6] - MediaTek has announced the completion of the design for its 2nm chip, the Dimensity 9600, which is expected to enter mass production by the end of next year [1][3] - By the end of 2026, several major companies, including Apple, Qualcomm, and Samsung, are expected to adopt 2nm technology [1][3] Group 2: Demand and Market Dynamics - TSMC's President, C.C. Wei, indicated that the demand for 2nm chips is unexpectedly high, surpassing that of 3nm chips [2][5] - Major clients such as Apple, AMD, and NVIDIA have already reserved TSMC's 2nm capacity, with Apple being the largest customer contributing 25.18% of TSMC's revenue in 2024 [3][5] - The performance improvements associated with the transition from 3nm to 2nm are driving significant interest from fabless companies [5][22] Group 3: Production Challenges - TSMC's production schedule for 2nm chips has faced delays, impacting the ability of smartphone manufacturers to incorporate these chips into their 2025 models [6][7] - The yield rates for 2nm chips are expected to start at around 70% and gradually improve, which may influence the timing of mass production for sensitive clients [10][11] - The complexity of transitioning to new technology nodes has led to longer timelines for product development, with the average time between nodes extending [19][21] Group 4: Competitive Landscape - The competition in the semiconductor foundry market is intensifying, with TSMC and Samsung both advancing their 2nm production plans [12][16] - TSMC is expected to have a monthly production capacity of 60,000 wafers by next year, while Samsung's capacity is reported to be significantly lower at 7,000 wafers [16][18] - The race for advanced manufacturing equipment, particularly high-NA EUV lithography machines, is critical for maintaining competitive advantage in the 2nm space [18][22] Group 5: Future Outlook - The transition from 2nm to 1nm technology is projected to take at least five years, with multiple iterations planned for the 2nm node [20][21] - Despite challenges, the semiconductor industry continues to innovate, with advancements in materials and packaging technologies expected to drive future transistor density improvements [22]

Core Insights - AMD's revenue share in the X86 server CPU market exceeded 40% and shipment share surpassed 27% in the first half of 2025, indicating stronger sales compared to Intel [2] - Despite Intel's challenges, AMD is projected to capture nearly 60% of the X86 server CPU revenue and over 72% of the shipment share in 2025 [2] - Intel's upcoming "Clearwater Rapids" and "Clearwater Forest" processors will rely on advanced manufacturing technologies, including the 18A process and 3D chip stacking techniques [2][3] AMD's Competitive Position - AMD's Epyc server CPUs are frequently released and dominate the market due to superior manufacturing processes from TSMC [3] - The competition in the data center market is intensifying as cloud builders increase their use of custom Arm server CPUs, with AMD being a strong competitor [3] Intel's Strategic Developments - Intel has the opportunity to regain some market balance with the launch of the 18A process and the new Xeon 7 processors, despite delays in product launches [3][4] - The introduction of the Clearwater Forest E-core processor is expected to enhance Intel's competitive edge [5] Technological Advancements - The 18A process technology offers a 15% performance improvement at the same power level and a 30% increase in chip density compared to previous processes [7] - The Clearwater Forest CPU features a 3D architecture that improves power efficiency and allows for higher transistor density [9] Performance Metrics - The Darkmont core in the Clearwater Forest architecture is designed to execute 17% more instructions per clock cycle compared to its predecessor [16] - The new architecture supports a total of 576 cores and 1,152 MB of L3 cache, significantly enhancing computational capabilities [26] Memory and I/O Capabilities - The Clearwater Forest platform boasts a memory bandwidth of 1300 GB/s and 96 PCI-Express 5.0 I/O channels, facilitating high data throughput [26] - The architecture allows for shared memory clusters between processors, enhancing performance in multi-processor configurations [26]