Core Insights - SK Hynix has unveiled its next-generation DRAM technology roadmap at the IEEE VLSI Symposium 2025, aiming to lead the company for the next 30 years [1][2] - The CTO emphasized the limitations of traditional technology platforms and the need for innovation in structure, materials, and components to overcome performance and capacity bottlenecks [1][2] Group 1: Next-Generation DRAM Technology - The 4F² VG platform minimizes DRAM cell area, achieving high density, speed, and low power consumption compared to traditional DRAM, which has a cell area of 6F [2] - The VG structure features a vertical gate, enhancing integration compared to the traditional horizontal gate structure [2] - 3D DRAM, which stacks memory cells vertically, is also a core direction for next-generation DRAM technology, with plans to overcome cost challenges through innovation [2] Group 2: Future Development and Collaboration - The CTO highlighted the importance of providing a mid- to long-term innovation roadmap for young engineers involved in future DRAM development [3] - SK Hynix aims to collaborate with the industry to realize the future of DRAM technology [3] - The company is also upgrading key materials and components to secure new growth momentum for the continuous evolution of DRAM technology over the next 30 years [2]

Core Viewpoint - NEO Semiconductor has announced a revolutionary new technology for DRAM memory, introducing two new 3D X-DRAM cell designs: 1T1C and 3T0C, which are expected to undergo concept validation testing by 2026. These designs can accommodate 512 Gb (64 GB) per module, ten times more than currently available modules, with a read/write speed of 10 nanoseconds and a retention time exceeding 9 minutes, addressing the bottlenecks in DRAM technology [1][3][20]. Summary by Sections 1T1C and 3T0C Overview - The new 1T1C unit integrates one capacitor and one transistor, utilizing a structure similar to 3D NAND to reduce manufacturing costs while enhancing data retention using IGZO (Indium Gallium Zinc Oxide) channels [5][9]. - The 3T0C unit integrates three transistors with IGZO channels, designed for current sensing operations, making it suitable for emerging memory computing and AI applications [16][46]. Performance and Efficiency - The 1T1C and 3T0C designs demonstrate unprecedented density, power efficiency, and scalability, with a retention time of up to 450 seconds and a significant reduction in refresh power [20][19]. - The technology allows for a bandwidth increase of 16 times while significantly lowering power consumption and heat generation, making it a transformative innovation for AI applications [19][20]. Manufacturing Process - The 3D X-DRAM technology is based on innovative floating body cell (FBC) technology, leveraging existing NAND processes for easy scalability and cost-effectiveness [19]. - The manufacturing process involves minimal modifications to existing DRAM production lines, ensuring faster development cycles and higher scalability [38][39]. Variants of 3D X-DRAM - The 3D X-DRAM technology platform now includes three variants: - 1T1C (one transistor, one capacitor) for high-density DRAM applications [43]. - 3T0C (three transistors, zero capacitor) optimized for current sensing, ideal for AI and memory computing [46]. - 1T0C (one transistor, zero capacitor) suitable for high-density DRAM and memory computing [46]. Industry Impact - NEO's CEO, Andy Hsu, stated that the introduction of 1T1C and 3T0C is redefining the possibilities of memory technology, breaking through the scaling limitations of current DRAM [44].