如果您希望可以时常见面，欢迎标星收藏哦~ 最近几年，RISC-V彻底火了。知名分析机构Omdia早前曾预测，到 2030 年，RISC-V 将占据整 个半导体市场的 25%，2030 年芯片出货量将达到 170 亿片。对于一个发展刚过十年的架构来说， 这个成长速度可谓惊人。 凭借拥有深厚经验积累的团队，隼瞻科技也正在成为这条赛道的一个重要玩家。但和我们熟悉的 RISC-V IP或者RISC-V芯片厂商不一样，隼瞻科技正在以期独特的服务模式，为产业提供支持。 " 我 们 是 一 家 以 RISC-V 为 基 础 ， 用 'IP + EDA' 组 合 产 品 为 行 业 提 供 处 理 器 整 体 解 决 方 案 的 公 司。"隼瞻科技创始人兼CEO曾轶在日前举办的湾芯展现场告诉半导体行业观察。 DSA，破局之法 熟悉芯片行业的读者都知道，这些所谓的处理器芯片大体来说其实可以分为两类，分别是通用芯片 和专用芯片。我们熟悉的无论是英特尔、AMD、英伟达或者高通的芯片，都是前者。但是，随着 产业的发展、需求的多样化和摩尔定律的放缓，这种通用的做法在一些任务上似乎开始逐渐捉襟见 肘。 在隼瞻科技的发展进程中，团队首先将 ...

Core Viewpoint - The development of AI is fundamentally changing the software programming paradigm, leading to the emergence of Software 3.0, where natural language prompts are replacing traditional programming code, and large language models (LLMs) are becoming the new programming interface [2][3]. Group 1: Software Evolution - Software 1.0 was characterized by human-written code, while Software 2.0 shifted to neural networks, requiring data preparation and parameter training [2]. - Software 3.0 represents a significant transformation in software development, driven by the rise of large language models [2]. - The transition to Software 3.0 necessitates advancements in hardware, referred to as Hardware 3.0, to support new computational demands [2][3]. Group 2: Hardware Requirements - The dominance of CPUs in Software 1.0 has shifted to GPUs in Software 2.0 due to the need for parallel processing capabilities [3]. - The rapid development of transformer-based models in Software 3.0 has led to the increased adoption of Domain-Specific Architectures (DSA) [5]. - A balance between specialized efficiency and programming generality is crucial for the development of Hardware 3.0 [5][8]. Group 3: Challenges in AI Processor Design - Key challenges in designing AI processors include the lengthy time required to construct AI computing architectures, the prolonged development of instruction systems, and the long cycles for compiling software [9]. - Achieving widespread ecosystem support for self-built instruction systems presents significant hurdles [9]. Group 4: RISC-V and EVAS Architecture - RISC-V's open and modular design allows for the customization of AI acceleration instruction sets, making it a suitable foundation for DSA [8]. - The introduction of the Virtual Instruction Set Architecture (VISA) aims to bridge the gap between AI compilers and backend compilation, enhancing performance optimization [10][11]. - The EVAS architecture integrates VISA with RISC-V microinstructions, ensuring efficient execution of AI computations while improving user programming experience [12][16]. Group 5: Upcoming Innovations - The upcoming chip from the company will support various data types, including INT4, INT8, FP8, FP16, and BF16, with a focus on mixed-precision computing [17]. - The new architecture aims to provide advanced computing solutions for applications in autonomous driving, embodied intelligence, and other edge-cloud industry applications, contributing to the progress towards AGI [17].