Core Viewpoint - The semiconductor industry is entering the "post-Moore era," where advanced packaging is crucial for overcoming chip performance bottlenecks, and EDA tools are central to the localization efforts in high-end packaging [1][2]. Group 1: EDA Solutions and Challenges - The 2.5D/3D stacking technology is essential for efficient integration of heterogeneous chips in fields like AI and 6G, but it brings increased complexity in the design process, including architecture planning, physical implementation, and testing [2][4]. - Traditional design methods face challenges such as tool fragmentation, long design iteration cycles, and difficulties in Chiplet interconnection testing, which hinder the pace of domestic advanced packaging [2][4]. Group 2: Silicon Chip Technology's EDA Platform - Silicon Chip Technology's 3Sheng Integration Platform addresses these challenges with a customized EDA solution that covers five key areas: architecture design, physical design, multi-die testing fault tolerance, analysis simulation, and multi-Chiplet integration verification [4][5]. - The platform enables full-process collaboration, breaking down tool fragmentation and improving simulation verification efficiency for 5nm chips by 30% [4]. - Real-time collaboration between design and simulation significantly shortens the iteration cycle, accelerating product market entry [4][5]. Group 3: Industry Collaboration and Forum - The "From Device to Network Collaborative Innovation Forum" on March 18, 2026, in Shanghai serves as a platform for showcasing technological achievements and facilitating precise supply-demand matching within the semiconductor industry [6][15]. - The forum aims to gather 200 key industry players, including major telecom operators and leading cloud service providers, to discuss collaboration needs and technological advancements in critical areas like compound semiconductors and EDA [6][15]. - Silicon Chip Technology plans to leverage the forum to demonstrate its 2.5D/3D EDA solutions and engage directly with decision-makers to explore customized needs in 6G and AI computing scenarios [10][15].

Core Viewpoint - The article discusses the advancements and challenges in the 2.5D/3D IC backend design EDA tools, emphasizing the need for collaborative innovation in the heterogeneous integration and advanced packaging sectors to meet the growing demands for AI computing power and overcome existing technological barriers [3][4][5]. Group 1: Event Overview - The "2025 TrendBank Heterogeneous Integration Packaging Industry Conference" was held on April 29, 2025, in Ningbo, co-hosted by TrendBank and Yongjiang Laboratory, with support from Zhuhai Silicon Core Technology Co., Ltd. and Ningbo Electronics Industry Association [1]. - Dr. Zhao Yi, founder and chief scientist of Zhuhai Silicon Core Technology Co., Ltd., delivered a keynote speech focusing on the EDA platform for 2.5D/3D advanced packaging, exploring collaborative innovation in backend design, simulation, and verification [1][3]. Group 2: Industry Insights - The demand for AI computing power has surged, outpacing the growth rate predicted by Moore's Law, leading to a conflict between increasing computational needs and the slow performance growth of chips [4]. - Advanced packaging technologies, such as stacked chips, allow for flexible integration and high-density interconnections, significantly enhancing integration levels and driving improvements in computing speed and storage capacity [4][5]. Group 3: Technical Challenges - The design complexity of stacked chips has increased exponentially, creating a scarcity of comprehensive EDA design toolchains that can address the new challenges in design, testing, and simulation [5]. - Key challenges in the 2.5D/3D Chiplet design field include achieving a cohesive top-level architecture, managing various packaging types, and understanding the benefits of architectural-level analysis [5]. Group 4: Solutions and Innovations - Zhuhai Silicon Core Technology has developed the 3Sheng Integration Platform, which provides a comprehensive solution covering the entire backend design process for Chiplets [5]. - The platform integrates five centers: architecture design, physical design, multi-die testing, analysis simulation, and multi-Chiplet integration verification, facilitating a collaborative design approach that maximizes performance, cost, and testability [5].