Core Viewpoint - The company held an earnings briefing on September 19, focusing on advancements in AI visual algorithms, semiconductor packaging and testing, technology iteration, humanoid robot layout, and export business growth [1][2]. Group 1: AI Visual Algorithms - The company has fully integrated AI algorithms into its machine vision products, such as AOI, SPI, AXI, and dispensing equipment, leading to significant improvements in product performance and market competitiveness [1]. - In semiconductor packaging, the accuracy of defect detection and false alarm control has notably improved, enhancing the precision of motion control for different PCB substrate states [2]. Group 2: Semiconductor Packaging Business - The company’s semiconductor packaging products focus on appearance defect detection for bonding and post-dicing processes, with small batch shipments already achieved [2]. - The 3D online X-ray inspection equipment (AXI) is currently undergoing validation testing with clients for internal defect detection in power devices, and the company has relevant technological reserves for advanced packaging [2]. Group 3: Technology Iteration - The company has fully adopted its self-developed AI algorithm models, which, combined with traditional algorithms, have enhanced the competitiveness of its machine vision products, leading to a continuous increase in product sales [2]. Group 4: Humanoid Robot Layout - The company possesses 3D structured light technology but has not yet industrialized its humanoid robot layout [2]. Group 5: Export Business Growth - In the first half of the year, the company’s export revenue reached 129 million, a significant increase from 77 million in the same period last year, driven by demand in consumer electronics and semiconductors [2]. - The growth in exports is attributed to market demand changes, global client expansion, and new overseas clients, as well as some domestic clients venturing abroad [2]. Group 6: Other Business Developments - The company’s cable assembly products are utilized in photolithography equipment, and its investment in the Suzhou Chip Dynamics Fund focuses on the semiconductor supply chain, yielding good project returns [2]. - The company’s detection equipment is applicable in the PCB industry, with major clients including well-known companies like Apple and Huawei, and the expansion of downstream client capacity is expected to boost demand for machine vision equipment [2].

尊敬的投资者，您好。公司已全面导入自主研发的 AI 算法模型， 极大提升了公司的机器视觉产品竞争力，市场反馈积极，相关 产品销量持续上升。目前主要以传统算法和 AI 算法相结合，未 来公司将全面转向 AI 算法。感谢您的关注。 证券代码：300802 证券简称：矩子科技 上海矩子科技股份有限公司投资者关系活动记录表 | | □ 特定对象调研 □ 分析师会议 | | --- | --- | | 投资者关系活 | □ 媒体采访 √ 业绩说明会 | | 动类别 | 新闻发布会 路演活动 □ □ | | | 现场参观 □ | | | □ 其他（请文字说明其他活动内容） | | 参与单位名称 | 投资者网上提问 | | 及人员姓名 | | | 时间 | 2025 年 9 月 19 日（周五）下午 15:00~17:00 | | 地点 | 公司通过全景网"投资者关系互动平台"（https://ir.p5w.net）采用 网络远程的方式召开业绩说明会 | | | 1、董秘：刘阳 | | 上市公司接待 | 2、财务总监：吴海欣 | | 人员姓名 | 3、董事长兼总经理：杨勇 | | | 4、独立董事：张浩 | | | 5、保 ...

Core Viewpoint - The company has fully integrated AI algorithms into its products, enhancing various operational processes such as component positioning, defect detection, and automatic programming [1] Group 1: AI Integration - The company has implemented AI algorithms across multiple products including AOI, SPI, AXI, and dispensing systems [1] - The applications of these AI algorithms are extensive, covering areas like component positioning, defect detection, and automatic programming [1] Group 2: Motion Control - The company has developed an adaptive transmission system for the MCB control board, utilizing deep learning algorithms [1] - This system allows for precise control based on the stop state of different PCB substrates [1]

Debugging Flows & Tools - The industry utilizes a four-step debug process: probing, implementing, analyzing, and fixing [1][2][3] - AMD provides ChipScope debug solution to reduce verification and debugging time, maximizing visibility into programmable logic during system operation [3] - Vivado Logic Analyzer (VLA) interacts with debug cores for triggering and data collection via JTAG pins, supporting various triggering scenarios and flexible probing [4] - Captured data can be reused as test vectors, enhancing design verification, and a single JTAG connection simplifies programming and debugging [5] - Debug cores like Integrated Logic Analyzer (ILA), System ILA, Virtual Input/Output (VIO), and JTAG to AXI Master enable design visibility without obstructing functionality [6] Debug Cores & Features - Integrated Logic Analyzer (ILA) IP core monitors internal signals with advanced features like Boolean trigger equations and edge transition triggers, configurable with up to 1024 probe ports [7] - Virtual Input/Output (VIO) core monitors and drives internal signals in real time, presenting data as virtual LEDs, pushbuttons, or toggle switches [9][10] - JTAG to AXI Master debug feature generates AXI transactions to interact with AXI-Full and AXI-Lite slave cores [11][12] - BSCAN to JTAG Converter core bridges BSCAN and JTAG interfaces for designs supporting JTAG but not BSCAN [13][14] Data Cables & Debug Ports - Platform Cable USB II is a general-purpose cable for programming and debugging, supporting devices with target clock speeds from 750 kHz to 24 MHz via USB 20 [15] - SmartLynq Data cable provides JTAG rates up to 40 Mb/s via Ethernet and USB, supporting JTAG debugging and indirect flash programming [16][17] - SmartLynq+ is designed for high-speed debugging and tracing in Versal Adaptive SoCs, offering trace capture speeds up to 10 Gb/s and up to 14 GB of trace memory [19][20] Probing Flows & Methodologies - HDL instantiation flow involves manual customization and connection of debug cores directly in the HDL design source, requiring re-running synthesis and implementation [22][23] - Netlist insertion flow inserts ILA cores directly into the netlist, eliminating design resynthesis and allowing probing at various design levels [23][24] - Incremental Compile Flow allows modifying debug cores while reusing 95% of prior placement and routing results [36] - ECO Flow focuses on replacing existing debug nets with minimal changes, preserving previous implementation results [37][38] ChipScoPy - ChipScoPy provides a Python interface to program and debug Versal devices, with a 100% Python code base available on githubcom [39] - ChipScoPy enables high-level control of Versal debug IPs, allowing developers to control and communicate with cores like ILA and VIO [39][40]

Core Viewpoint - The management of chip resources is becoming a significant and multifaceted challenge as chips move beyond proprietary designs of large manufacturers and interact with other elements in packaging or systems [1] Group 1: Chiplet Market Dynamics - The chiplet market is currently dominated by monopolistic suppliers, with approximately 95% to 99% of the market controlled by one or a few suppliers adhering to specific specifications [3] - There are three main markets for small chips: exclusive markets, local ecosystems, and open markets, with local ecosystems consisting of five to seven companies collaborating on interoperability [3][6] - Major system and processor suppliers have effectively utilized chiplet approaches to enhance performance and reduce costs through increased computational density [1][3] Group 2: Design and Interoperability Challenges - Many companies are struggling with interoperability and generality, often starting their work from within the chip rather than from a system perspective [2] - The complexity of integrating third-party chips into systems is a significant challenge, requiring time and effort to resolve [1][2] - The need for a common system bus across all chipsets is emphasized, as it adds complexity for IP suppliers who must adapt to changing customer needs [2][3] Group 3: Resource Management and Optimization - Effective resource management is crucial as poor management can lead to performance bottlenecks, increased development costs, and challenges in power consumption [1] - The industry is transitioning from exclusive ecosystems to local ecosystems, with companies seeking the best methods for chip construction [6] - Simplifying chip design through partitioning based on technology can help manage complexity and improve performance [6][7] Group 4: Future Directions and Innovations - The chip industry is beginning to explore open chip economies, allowing for plug-and-play capabilities from multiple suppliers within a single package [11][12] - There is a growing recognition of the need for robust verification IP to ensure interoperability among chiplets, which is currently lacking in the industry [9][10] - The challenge of managing thousands of chips in a single package requires a comprehensive approach to resource management and system integration [12]