Summary of Key Points from the Conference Call Industry Overview - **Industry Focus**: The conference call primarily discusses the semiconductor industry, specifically the advanced packaging segment and the adoption of chiplet architectures. - **Key Technologies**: Emphasis on CoWoS (Chip-on-Wafer-on-Substrate) and FOCoS (Fan-Out Chip on Substrate) technologies as critical for advanced packaging solutions. Core Insights and Arguments - **Chiplet Adoption**: The adoption of chiplet architectures is accelerating, particularly as the industry transitions to 2nm nodes. Projections indicate chiplet penetration for nodes 5nm and below will reach 21% in 2025, 30% in 2026, and 37% in 2027, with 2nm node adoption expected to reach 57% by 2027E [1][40]. - **Cost and Yield Improvements**: Chiplet architectures can significantly lower manufacturing costs by splitting larger dies into smaller ones, improving yield rates. For instance, manufacturing costs can be reduced by 79.2% when transitioning from a single large die to multiple smaller chiplets [1][24][36]. - **Growing Demand for CoWoS**: The increasing chiplet penetration is expected to drive demand for CoWoS technology, which facilitates high-speed die-to-die interconnections. This demand is projected to grow at a CAGR of 71% for capacity and 63% for shipments from 2025 to 2027E [1][54][55]. Company-Specific Insights - **TSMC (2330.TW)**: - TSMC is a leader in advanced semiconductor packaging, particularly through its CoWoS technology, which is essential for AI and HPC applications. The company is expected to see significant revenue growth from CoWoS, with projections indicating it will account for 8.3% to 15.3% of TSMC's revenue from 2025 to 2027E [1][66]. - TSMC's CoWoS capacity is forecasted to reach 75k, 120k, and 170k in 2025, 2026, and 2027, respectively, reflecting aggressive capacity expansions to meet demand [1][66]. - **ASE (3711.TW)**: - ASE is gaining traction with its FOCoS technology, which is a cost-effective alternative to CoWoS, typically priced at half the cost. ASE's revenue from advanced packaging is expected to grow by 15% and 11% YoY in 2025 and 2026, respectively [1][67][69]. - **All Ring (6187.TWO)**: - All Ring is positioned to benefit from the advanced packaging trend, with expectations of revenue growth of 42% and 18% in 2025 and 2026, driven by CoWoS capacity expansion and new opportunities in CPO (Co-Packaged Optics) [1][71]. - **GPTC (3131.TWO)**: - GPTC is a key supplier of wet processing equipment for advanced packaging, with a market share of approximately 50% at TSMC. The company is expected to see revenue growth of 18.7% CAGR from 2024 to 2027, driven by the complexity of advanced packaging technologies [1][74][90]. Additional Important Insights - **Market Dynamics**: The report highlights the shift from traditional packaging methods to advanced solutions like CoWoS and FOCoS, indicating a broader market trend towards higher integration and performance in semiconductor designs [1][53]. - **Total Addressable Market (TAM)**: The total addressable market for CoWoS is projected to reach US$27.8 billion by 2027, growing at a CAGR of 65% from 2025 to 2027E [1][55][60]. - **Risks and Challenges**: Key risks include potential deterioration in end-demand, competition, and execution challenges that could impact profitability and market share for the companies involved [1][80][85][89]. This summary encapsulates the critical insights and projections discussed in the conference call, focusing on the semiconductor industry's evolution towards advanced packaging technologies and the implications for key players in the market.

Core Viewpoint - The demand for Chiplet architecture is increasing due to advancements in cloud computing, high-performance computing (HPC), and artificial intelligence (AI), alongside rising technical challenges and costs in semiconductor design and manufacturing [1][3]. Group 1: UCIe Alliance and Standards - The Universal Chiplet Interconnect Express (UCIe) Alliance was established in 2022 by major semiconductor companies and cloud service providers to create standardized interconnect specifications for Chiplets, enhancing flexibility, efficiency, and customization [1]. - UCIe 3.0 was recently launched, featuring enhancements in power efficiency and management while maintaining backward compatibility, and it supports data rates of 48 GT/s and 64 GT/s, doubling the bandwidth of the previous UCIe 2.0 [3][5]. Group 2: Performance and Applications - The performance improvements in UCIe 3.0 are particularly aimed at meeting the "insatiable demand for high bandwidth" in rapidly expanding fields such as AI, HPC, and data analytics, where interconnect boundary lengths are limited [3][5]. - The new data rates apply to both UCIe-S (2D standard packaging) and UCIe-A (2.5D advanced packaging) designs, addressing the need for higher throughput within constrained interconnect boundaries [5][9]. Group 3: Technical Specifications - UCIe 3.0 introduces new data rates of 48 GT/s and 64 GT/s, with specific characteristics for UCIe-S and UCIe-A, including bandwidth density and power efficiency targets [9]. - The standard maintains backward compatibility to ensure seamless integration with existing systems and infrastructure, allowing for a smooth transition for system designers and developers [7][9]. Group 4: Broader Implications - The Chiplet architecture is becoming ubiquitous across various sectors, including mobile devices, PCs, and automotive applications, with UCIe expected to cover a complete computing continuum from handheld devices to data centers [10]. - UCIe 3.0 also includes improvements such as runtime recalibration for low-power link tuning and more flexible Session Initiation Protocol (SIP) topologies, enhancing its applicability in new interconnect scenarios [10].

Core Viewpoint - The article discusses the transition from custom chip environments to standardized chiplet designs, emphasizing the need for a robust ecosystem to support this shift [2][4]. Group 1: Chiplet Design and Ecosystem - The importance of application-specific chiplets is highlighted, suggesting that proper system segmentation can enhance efficiency and specialization [4]. - The concept of a "chip ecosystem" is introduced, indicating that it encompasses more than just purchasing chips; it involves a comprehensive infrastructure [5][6]. - The article notes significant advancements in EDA capabilities and standards, which have improved the integration and testing of chiplet systems [5][6]. Group 2: Challenges and Solutions - Key challenges in chiplet design include thermal performance, electromagnetic interference, and stress management, which require new models for integration [8][9]. - The lack of standardized packaging sizes and interfaces is identified as a barrier to effective chiplet integration [9][10]. - The article emphasizes the need for improved interconnect analysis to enhance predictability and reduce computational costs in chiplet design [14]. Group 3: Market Dynamics and Future Outlook - Companies are increasingly seeking cost efficiency, customization, and configurability in chiplet designs, driving the demand for multi-chip and chiplet systems [6][7]. - The article mentions that traditional semiconductor companies are now facing competition from automotive OEMs and emerging tech firms in the chiplet space [13]. - The vision for a chiplet ecosystem includes collaboration across hardware, software, protocols, and EDA processes to accelerate development [13].

Core Viewpoint - The semiconductor industry is experiencing a significant shift towards chiplet architecture, which allows for the integration of multiple smaller chips into a single package, addressing the challenges of high costs and scalability associated with traditional single-chip designs [2][4][8]. Group 1: Chiplet Technology Overview - Chiplets are designed to be combined into a single package, enabling the creation of larger and more complex systems than traditional single-chip designs [4][8]. - The architecture allows for the separation of I/O and logic functions, optimizing performance and cost by utilizing different manufacturing nodes for various components [4][5]. - Examples include Nvidia's Blackwell B200 GPU, which employs a dual-chiplet design to exceed the limitations of single-chip designs [5]. Group 2: Advantages of Chiplet Architecture - Chiplet architecture can achieve higher yields and lower overall manufacturing costs by utilizing smaller chips [14]. - It allows for the integration of diverse processing elements, such as CPUs, GPUs, and memory controllers, enhancing design flexibility and performance [14]. - The modular nature of chiplet designs supports platform-based design and design reuse, making it easier to adapt to different applications [14]. Group 3: Challenges and Ecosystem Development - The chiplet ecosystem is still developing, with challenges in establishing universal standards for inter-chip communication, such as UCIe and CXL [10][11]. - Effective D2D communication must achieve low latency and high bandwidth across various physical interfaces, complicating system integration [10]. - The long-term vision for a complete chiplet ecosystem involves the seamless integration of pre-validated chiplets from trusted suppliers, which is still years away from realization [11][12]. Group 4: Current Industry Landscape - Major companies like AMD, Intel, and Nvidia are leading the development of multi-chip systems, while smaller firms are forming micro-ecosystems to leverage existing standards [13]. - Collaboration among EDA and IP vendors is crucial for developing standards and tools necessary for chiplet integration [13]. - Despite the hype surrounding chiplet technology, a fully functional chiplet ecosystem may take five to ten years to establish, although companies are already beginning to implement chiplet-based designs [13].

Investor Presentation | Japan M Foundation Japan Summer School: Semiconductor Production Equipment June 13, 2025 03:18 AM GMT Morgan Stanley MUFG Securities Co., Ltd.+ Tetsuya Wadaki Equity Analyst Tetsuya.Wadaki@morganstanleymufg.com +81 3 6836-8890 Semiconductor Production Equipment Japan Industry View Attractive Morgan Stanley does and seeks to do business with companies covered in Morgan Stanley Research. As a result, investors should be aware that the firm may have a conflict of interest that could aff ...

Group 1: Semiconductor Manufacturing Trends - Manufacturing utilization rates continue to improve year-on-year, with downstream manufacturers focusing on Chiplet and advanced packaging technologies[1] - The storage market is showing signs of a price turning point, with an upward trend expected to continue until Q3 2025, driven by AI-related demand[1] - Design companies are experiencing differentiated downstream demand, with power and analog companies reporting a recovery in industrial and automotive sectors[1] Group 2: Equipment and Domestic Production - Global WFE is projected to reach $100 billion in 2025, with a year-on-year growth of 4%-5%[3] - Domestic equipment manufacturers are seeing significant growth in new orders, benefiting from downstream expansion and increased localization rates[3] - The verification speed of core new equipment by domestic companies is accelerating, indicating a positive trend for advanced node domestic equipment breakthroughs[3] Group 3: Storage Market Dynamics - The storage market is expected to see price increases, with predictions of 18-23% and 13-18% growth for Server and PC DDR4 modules respectively in Q2 2025[4] - The enterprise storage market is projected to grow from $23.4 billion in 2024 to $49 billion by 2028, reflecting a compound annual growth rate (CAGR) of 16%[25] - Domestic manufacturers are positioned to benefit from the increasing demand for enterprise-level storage driven by AI infrastructure investments[25] Group 4: Design Sector Insights - The power semiconductor sector in China is entering a mild upward cycle, with a 14.5% year-on-year increase in domestic passenger car production from January to April 2025[38] - The demand for SoC and MCU products is significantly driven by national subsidies and export opportunities, with performance expected to vary across companies in Q2 2025[26] - The analog chip sector is recovering, with industrial and communication sectors seeing a return to inventory restocking[29]

Core Viewpoint - Modern automobiles are evolving into "data centers on wheels," necessitating high-performance computing that can operate reliably under harsh conditions for 10-15 years [1][2]. Group 1: Automotive Computing Needs - The automotive industry requires not only mobility but also autonomy, safety, and continuous software updates, leading to a sustained demand for high-performance computing [1]. - The environment in which automotive systems operate is fundamentally different from that of data centers or smartphones, necessitating robust design [1]. Group 2: Role of imec - imec is positioned at the forefront of integrating mobility and microelectronics, leveraging Europe's strong automotive tradition and semiconductor strategy [2]. - The organization is conducting cutting-edge research to prepare for automotive-grade industrial applications, focusing on advanced packaging, chip architecture, and system integration [2]. Group 3: Chiplet Technology - Chiplet technology, which consists of small modular processing units, is being considered for automotive applications to meet the performance demands of autonomous and connected vehicles [3]. - The advantages of Chiplet include higher yield, cost-effectiveness, architectural flexibility, and heterogeneous integration, although challenges remain regarding long-term reliability in harsh environments [3]. Group 4: Sensor Development - imec's SENSAI project is advancing next-generation sensor technologies, including CMOS cameras and solid-state LiDAR, to enhance vehicle intelligence [4][5]. - A digital twin framework is being developed to simulate sensor configurations, helping to reduce costs and accelerate development without the need for physical prototypes [4]. Group 5: Collaborative Ecosystem - A collaborative ecosystem is essential for the successful integration of chips and sensors in vehicles, as highlighted by imec's STAR program, which aims to standardize interfaces and protocols among automotive manufacturers and semiconductor companies [5]. - The STAR program is focused on establishing consensus through workshops and forums to lay the groundwork for economies of scale in the automotive sector [5].

如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容 编译自 semiengineering 。 多芯片组装的发展以及边缘传感器数据价值的不断增加开始引起人们的关注，并引发了人们对模拟 电路安全性的质疑。 在当今大多数SoC设计中，安全性几乎完全是一个数字问题。数字电路的安全性要求已广为人知， 尤其是在大型数据中心和边缘计算的高端领域，这些领域以数字计算为主导。这在很大程度上是由 于片上空间有限，因为模拟电路无法扩展。即使是混合信号IP也已逐渐数字化，以便能够容纳更小 的空间。但随着行业从平面SoC转向多维、异构系统级封装（SiP，包括2.5D、3D和3.5D），这些 面积限制已经放宽。 这并没有让模拟电路的集成变得更容易，但工艺节点和尺寸已不再是最紧迫的问题。模拟芯片可以 在任何合理的节点上开发，并且仍然可以装入封装中，而封装的尺寸可以调整到合适的大小以容纳 更大的芯片。这反过来也有助于提高模拟元件的复用率。 还有其他好处。由于其中一些电路可以更独立地运行——SiP 可以是异构的，并且可以全局异步 ——它们应该能够比现在更容易地插入多芯片组件。此外，额外的面积可以帮助减轻对平滑模拟波 的干扰，而这对于隔离嘈 ...

先进封装成为下１个技术帝国的边疆要塞，不是偶然，而是3股力道推动出来的必然结果。 第1股力道是算力井喷，但制程进展放缓，芯片必须被切割、堆叠、重组。陆行之表示，你能做到 5奈米，不代表你能塞进20倍算力，光罩极限挡住了芯片的面积，只有Chiplet 能绕过这道墙， Ncidia Blackwell 就是这样诞生的。 第2股力道则是应用百变，芯片不再单一适配，系统设计走向模组化。陆行之说，1种芯片搞定所 有应用的时代已经结束，AI训练、自驾决策、边缘运算、AR装置……每1个应用都需要不同组合 的矽，先进封装加Chiplet，就是设计弹性与效率的平衡解答。 如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容来自 自由时报 。 半导体的改变正在加速，先进封装，不再是边角料。知名分析师陆行之表示，棋盘中央如果说先进 制程是矽时代的权力中枢，那么先进封装，正在成为下１个技术帝国的边疆要塞。 陆行之在脸书上贴文指出，10年前，这条路线曾被误解，甚至被忽视，但10年后的今天，它已悄 悄从「非主流的Plan B」变成「主流赛道的Plan A」。 第3股力道则是资料搬运成本飙升，能耗变成第１瓶颈。在AI 芯片里，搬资料的耗能 ...

Core Insights - The article discusses the challenges and solutions related to the transition to Chiplet and 3D-IC technologies in the semiconductor industry, emphasizing the importance of standards and collaboration among companies [3][5][6]. Group 1: Challenges in Semiconductor Integration - Leading chip manufacturers have limited options for 2D scaling, prompting a shift towards multi-chip components and Chiplet integration [5]. - The integration of different chips poses significant challenges, including ensuring reliability and yield, which is more complex than traditional 2D design processes [6][7]. - The industry faces bottlenecks in integrating process and packaging technologies, as well as testing these complex chips [6][7]. Group 2: Importance of Standards and Collaboration - The concept of a "chiplet economy" is emerging, where various suppliers provide chips that are integrated into 3D-IC systems, creating both opportunities and challenges [5]. - Standards are crucial for reducing costs and improving efficiency, allowing companies to share the burden of technology development [6][9]. - The need for a unified platform that integrates different technologies and standards is highlighted as essential for successful Chiplet integration [11]. Group 3: AI and Productivity Challenges - The demand for AI-driven solutions is increasing as companies face productivity challenges in integrating chips and meeting market demands [7][8]. - Traditional scaling methods are becoming less effective, necessitating innovative approaches to bridge the productivity gap [8]. Group 4: Thermal Management Solutions - Effective thermal management is critical for the performance of 3D-ICs, with various cooling technologies such as microfluidics and immersion cooling being explored [11][12]. - Designers must consider thermal issues from the outset of the design process, integrating cooling solutions into the chip design [12][13].