Core Viewpoint - The article discusses the evolution of integrated circuits (IC) driven by rapid advancements in AI computing power and increasing demand for high-bandwidth interconnects, highlighting a cyclical trend of "separation and integration" in the industry [2]. Group 1: Industry Trends - The transition from single chips to larger-scale System on Chips (SoC) and then to Chiplet/multi-die configurations is emphasized as a key trend in IC evolution [2]. - The industry is entering a post-Moore's Law phase, where advanced packaging and heterogeneous integration are critical, necessitating tighter collaboration across the supply chain to address system-level constraints [2]. Group 2: Forum Details - On March 26, a forum titled "From Ecological Construction to Application Landing: Chiplet and Advanced Packaging Industry Collaboration" will be held, organized by Silicon Chip Technology in collaboration with various industry partners [2][6]. - The forum aims to connect representatives from design, manufacturing, testing, equipment, EDA, and application sectors to focus on the engineering implementation path of standards, chiplet libraries, and next-generation 2.5D/3D EDA toolchains [2][6]. Group 3: Forum Highlights - The forum will showcase advanced packaging industry collaborative application solutions based on typical case studies, demonstrating how to translate standards and collaboration mechanisms into executable engineering processes [9]. - A session will be dedicated to the establishment of advanced packaging standards by the China Electronics Standardization Association, aiming to move from discussion to actionable engineering rules [10]. Group 4: Collaborative Opportunities - The event will facilitate discussions among representatives from design, manufacturing, testing, materials, equipment, EDA, and application sectors to align key requirements and collaboration boundaries, thereby reducing information discrepancies across different stages [11]. - Through roundtable discussions and on-site exchanges, the forum aims to promote joint verification and supply-demand matching, creating concrete opportunities for future project collaborations [11].

Core Viewpoint - The article discusses the evolution and significance of Chiplet technology in accelerating AI development, highlighting its advantages over traditional chip designs [2][20]. Group 1: Chiplet Definition and Evolution - Chiplet design is defined as multiple chips within the same package that communicate using signals optimized for intra-package communication [4]. - The evolution of chip technology includes multi-chip modules (MCM), multi-chip packages (MCP), and various advanced packaging techniques such as NAND flash stacking and AMD's VCache technology [2][4]. Group 2: Advantages of Chiplet Technology - Chiplets allow for the division of large designs that cannot fit on a single chip due to reticle size limitations [4]. - Smaller Chiplets improve yield rates compared to larger chips, making them more cost-effective [4]. - Advanced process node costs can range from $30 million to $50 million, and Chiplets help limit the use of expensive nodes to profitable areas [4]. - Chiplets facilitate the generation of more SKUs and accelerate time-to-market with lower non-recurring engineering costs [5][6]. - They enable the mixing of different wafer technologies, such as memory and logic circuits [5]. - Some technologies, like SRAM, do not scale down with process nodes, making Chiplets a viable solution [5]. - Chiplets can lead to energy savings [5]. Group 3: Economic Impact and Market Predictions - The use of Chiplets is exemplified by Xilinx's large FPGA manufacturing, which demonstrates their economic advantages for large applications, especially in AI [9]. - AMD's multi-chip designs, such as Zen 5 and Zen 5c, illustrate the economic production of new SKUs by utilizing different core chips [13]. - The article predicts that the chip market will reach $600 billion by 2031, driven by significant capital expenditures in AI systems [20].

Core Insights - The semiconductor industry is shifting focus from miniaturization of individual chips to the integration of multiple smaller units, known as Chiplets, due to physical limitations in chip size and yield issues [2][6][9] - The demand for larger AI models necessitates an increase in transistor count on chips, leading to a need for larger chip sizes, which is constrained by current lithography technology [5][6] - The industry is exploring new materials and architectures, particularly glass substrates, to overcome the limitations of organic substrates and silicon interconnects [24][28][33] Group 1: Chiplet Architecture - Chiplet architecture allows for the assembly of smaller chips, improving yield and reducing costs while enabling the use of different manufacturing processes for various components [9][10] - The communication between Chiplets must be efficient; otherwise, the benefits of separating chips could be negated [10][11] - Companies like NVIDIA and Intel are already implementing Chiplet designs in their products, such as NVIDIA's Blackwell and Intel's Ponte Vecchio [9] Group 2: Material Limitations - Organic substrates have dominated the market for 25 years but are now facing challenges in high-performance applications, particularly in AI chips [15][16][20] - Silicon interconnects provide superior performance but come with high costs and resource constraints, leading to a bottleneck in production capacity [21][22][49] - Glass substrates are being explored as a potential solution, offering advantages in thermal expansion matching and signal integrity [28][29][30] Group 3: Glass Substrate Development - Two main approaches for glass substrates are emerging: replacing the interconnect layer with glass and using glass as a substrate itself [26][27] - Glass has shown superior performance in thermal expansion and signal loss compared to organic materials, making it a promising alternative [28][29] - However, challenges such as fragility, thermal conductivity, and power noise must be addressed before glass can be widely adopted [31][32][33] Group 4: Competitive Landscape - Intel has invested heavily in glass substrate technology and holds a significant number of patents, but recent leadership changes raise questions about its future in this space [36][38] - Samsung is pursuing a vertically integrated approach to glass substrate production, but quality issues have been reported with their prototypes [39] - Other companies, such as Absolics, are also entering the market but face challenges in securing large customers for their products [40] Group 5: Industry Dynamics - The semiconductor industry is at a crossroads, with multiple technologies competing for dominance in the substrate and interconnect space [52][53] - The future will depend on the ability to achieve high production yields and meet the demands of AI chip growth, with no clear winner emerging yet [35][58] - The ongoing developments in both glass and organic materials will shape the competitive landscape, with significant implications for production capabilities and market dynamics [57][60]

Core Insights - The semiconductor industry is projected to reach a record sales figure of $975 billion by 2026, driven primarily by the growth of artificial intelligence infrastructure [3] - The industry faces a paradox where strong demand from AI is pushing revenues to unprecedented heights, but there are significant risks associated with over-reliance on AI [2] - By 2026, AI chips are expected to contribute nearly 50% of total industry revenue, yet their production volume remains low, accounting for only 0.2% of total chip sales [6][7] Market Conditions - The semiconductor industry's growth rate is expected to accelerate from 22% in 2025 to 26% in 2026, with long-term projections indicating sales could reach $2 trillion by 2036 [6] - The total market capitalization of the top ten semiconductor companies reached $9.5 trillion by December 2025, a 46% increase from the previous year [6] - The revenue from generative AI chips is forecasted to approach $500 billion by 2026, representing a significant portion of global chip sales [6] Supply and Demand Dynamics - The average selling price of chips is projected to be $0.74, with total chip sales expected to reach 1.05 trillion units by 2025 [7] - Memory revenue is anticipated to reach approximately $200 billion in 2026, constituting 25% of total semiconductor revenue [7] - The semiconductor industry is experiencing a supply-demand imbalance, particularly in memory components, leading to significant price increases [8][26] Strategic Considerations - Companies must consider how to maintain high cash levels and low debt while fulfilling capital expenditure commitments in the face of potential demand slowdowns for AI chips [11] - The industry is urged to explore alternative markets if demand for AI chips declines, as well as to reassess the allocation of advanced memory and logic manufacturing capabilities [12] - The rise of vertical integration among AI, semiconductor, and cloud infrastructure providers indicates a new cycle of capital investment in AI computing [21] Geopolitical and Economic Factors - Geopolitical tensions are influencing semiconductor investments, with governments seeking to enhance local manufacturing capabilities for national security and supply chain resilience [22] - The global economic outlook remains strong, with growth rates of 3.2% in 2025 and 3.1% in 2026, yet capacity constraints in semiconductor manufacturing could overshadow technological advancements [25] - The semiconductor industry is facing challenges related to material shortages and production capacity, which could hinder growth despite strong demand for AI-related products [28][27]

Core Viewpoint - Heshun Petroleum (603353) is actively pursuing the acquisition of Shanghai Kuixin Integrated Circuit Design Co., with ongoing due diligence and a focus on the Chiplet sector, which is expected to see significant growth in the coming years [1][2][3] Group 1: Company Performance - As of January 9, 2026, Heshun Petroleum's stock closed at 27.81 yuan, up 1.76% from the previous week [1] - The company's total market capitalization is 4.781 billion yuan, ranking 18th out of 30 in the refining and trading sector and 3594th out of 5182 in the A-share market [1] Group 2: Acquisition and Strategic Focus - The acquisition of Kuixin Technology is progressing, with a focus on high-speed interconnect IP and Chiplet solutions, which are critical for high-performance computing [1][2] - Kuixin Technology's Chiplet clients include leading domestic AI chip companies, with products aimed at large model training and scientific computing, expected to achieve mass production in the second half of next year [1][3] Group 3: Future Growth and Market Demand - Kuixin Technology is experiencing a positive growth trend in 2025, with increasing order volumes and stable expansion of core IP and Chiplet solutions [2][3] - The company's future growth will be driven by three main business lines: steady growth in IP business, expansion of AI SIC mass production services, and potential growth from Chiplet and IO Die technologies [2][3]

Core Insights - The report from Jinyuan Securities highlights the exponential growth in costs associated with advanced processes in the semiconductor industry, particularly noting that the design cost of a 2nm chip is approximately $725 million, which is 25 times that of a 65nm chip [1][2] - Capital expenditures (CapEx) for building semiconductor manufacturing facilities also reflect this trend, with the investment required for a 5nm chip factory being five times that of a 20nm factory [1][2] Advanced Packaging Trends - The shift towards advanced packaging is driven by the combination of chiplets and high-end advanced packaging, which allows for mixed processes, reduced time to market, reusability, and improved yield [2] - Chiplets can utilize different processes based on demand, such as using 3nm technology for CPUs while employing mature processes for I/O or analog circuits, thus shortening R&D cycles and design costs [2] - The performance per watt per dollar (Perf/Watt/Dollar) indicates that large chips combined with 3D stacking are more suitable for medium and small systems, while complex systems benefit from the "small die with better yield" approach [2] AI Chip Performance - In terms of raw computational performance, AI-specific chips (ASICs) are weaker than AI GPUs, and even large language models like GPT-4 cannot run on a single chip [3] - To match the performance of AI GPUs, ASICs require larger clusters of dedicated chips, and advanced packaging through chiplets and heterogeneous integration is key to maximizing performance while controlling costs [3] Technological Evolution in Advanced Packaging - The core of technological evolution in advanced packaging is the continuous increase in interconnect I/O count and bandwidth density, transitioning from high-density electronic interconnects to incorporating optical interconnects [4] - The second generation of packaging aims to support higher interconnect I/O demands in the AI era, addressing bandwidth and power consumption bottlenecks [4] 2.5D Packaging Technology - Silicon bridge packaging technology serves as a 2.5D solution, integrating one or more silicon bridges within a specific packaging substrate to ensure interconnectivity between multiple chips [5] - The main factors limiting 2.5D interconnect density include solder bridging risks, intermetallic compounds, and underfill process challenges [5] - Direct bonding and hybrid bonding techniques are crucial for enhancing interconnect density by eliminating solder layers and achieving closer interconnect spacing [5] Advanced Packaging Market Outlook - The advanced packaging market in China is projected to reach approximately 96.7 billion yuan in 2024, accounting for 30.95% of the global market, with expectations to grow to 188.8 billion yuan by 2029, reflecting a compound annual growth rate (CAGR) of 14.30% [7] - By 2029, China's advanced packaging and testing market is anticipated to represent 36% of the global market size [7] - The unit packaging cost is higher due to the complexity of processes and the use of silicon interposers and embedded silicon bridge technology [7] Related Companies - Equipment manufacturers include Tuojing Technology (688072.SH), Zhongwei Company (688012.SH), Shengmei Shanghai (688082.SH), Guangli Technology (300480.SZ), Beifang Huachuang (002371.SZ), and Zhongke Feimiao (688361.SH) [7] - Material suppliers include Dinglong Co., Ltd. (300054.SZ), Anji Technology (688019.SH), and Feikai Materials (300398.SZ) [7] - OSAT companies include Shenghe Jingwei (unlisted), Changdian Technology (600584.SH), and Shenzhen Technology (000021.SZ) [7]

Core Viewpoint - The article discusses the differences between chiplets and soft IP, emphasizing that while both can accelerate time-to-market, they serve different needs and come with distinct challenges in design, integration, and testing [2][20]. Group 1: Chiplet vs Soft IP - Chiplets can be seen as a new type of semiconductor IP, but they differ significantly from the current IP licensing ecosystem, particularly in design integration and verification [2][20]. - Chiplets can be either custom-designed or off-the-shelf, with two camps emerging: one that designs its own chiplets and another that sources components externally [2][20]. - The market for chiplets will coexist with custom chips, with many IP modules becoming off-the-shelf chips that system vendors can mix and match [2][20]. Group 2: Customization and Functionality - The key difference between chiplets and soft IP lies in their customizability; soft IP offers high configurability, while chiplets have fixed functionalities [6][20]. - Chiplets require careful management of startup processes and debugging, which are less of a concern with soft IP [6][20]. - The physical integration of chiplets presents unique challenges, such as managing signal integrity and power distribution, which are not as critical in soft IP [24][20]. Group 3: Testing and Supply Chain - Testing chiplets is more complex than testing soft IP, as chiplets are typically tested independently by suppliers, requiring integration into the overall system testing process [20][20]. - The supply chain for chiplets is more traditional and complex, closely tied to manufacturing nodes and foundries, which increases dependency on suppliers [20][20]. - Built-in self-test (BiST) technology is expected to become more prevalent to address the transparency issues associated with chiplets [22][20]. Group 4: Security and Integration Challenges - Security considerations for chiplets are more challenging than for soft IP, as chiplets have a larger attack surface due to their interconnections and shared resources [20][20]. - Each chip in a multi-chip system must coordinate its security measures, which can lead to inefficiencies if not managed properly [20][20]. - The physical design of chiplets must account for thermal management and signal integrity, requiring advanced modeling tools that go beyond those used for soft IP [24][20].

Core Insights - The global semiconductor market is approaching the $1 trillion mark, driven by explosive demand for AI computing power and accelerated domestic supply chain autonomy, indicating a new growth cycle for the semiconductor industry [1] Group 1: Market Growth and Trends - The global semiconductor market is projected to grow over 25% year-on-year by 2026, reaching $975 billion, marking a strong recovery from previous inventory reductions [1] - AI is identified as the core engine of the current semiconductor cycle, with Huawei predicting a 100,000-fold increase in total computing power by 2035, leading to massive demand for chips and high-end storage [1] Group 2: Storage Industry Dynamics - The AI revolution is fundamentally altering the traditional cycle logic of the storage industry, with exponential growth in data throughput due to advancements in large models and complex reasoning [2] - There is a significant supply-demand gap in the conventional storage market as major manufacturers like Samsung and SK Hynix prioritize capacity for high-bandwidth memory (HBM), with DRAM prices expected to rise by 13-18% by Q4 2025 [2] - The global HBM market is forecasted to have a compound annual growth rate of 33% from 2024 to 2030 [2] Group 3: Domestic Semiconductor Development - China's semiconductor industry is advancing towards core areas of autonomy, particularly in semiconductor equipment and storage chips, with significant breakthroughs in funding and technology [2] - The year 2025 is anticipated to be critical for the growth of domestic equipment orders and performance realization, particularly for leading companies in etching and thin-film deposition [3] Group 4: Investment Opportunities - Investment opportunities in the semiconductor sector can be categorized into two main lines: AI-driven innovation and deepening domestic processes [3] - Key companies benefiting from AI demand include domestic design firms like Cambricon and Haiguang Information, as well as storage companies such as GigaDevice and Jiangbo Long [3][4] - In the semiconductor equipment sector, companies like North Huachuang and Zhongwei Company are highlighted for their breakthroughs in critical processes [3][4] - A comprehensive focus on the entire semiconductor supply chain is recommended, with key players including SMIC and Hua Hong Semiconductor [3][4]

Core Insights - AI is identified as a new driving force for the future of the semiconductor industry, transitioning from traditional computing to AI applications, which are still in the foundational stage but will diversify significantly in the coming years [2][3] - The shift towards AI applications will challenge traditional chip design economies of scale, necessitating new approaches such as Chiplet architecture to manage development costs and enhance market flexibility [3] - Advanced packaging technologies are becoming critical for performance enhancement, with a focus on system design as a key area for future development in the semiconductor sector [3] Group 1 - AI is redefining the meaning of Moore's Law, moving from centralized data centers to edge computing and AIoT applications, which will include smart cars, robots, smart homes, and smart cities [2] - The cost of designing advanced chips, such as TSMC's products below 5nm, can reach approximately $2 billion, making it unfeasible for companies to invest heavily without guaranteed sales [3] - The Chiplet concept allows for modular design, enabling the reuse of high-performance modules across various products, thus distributing development costs and increasing market adaptability [3] Group 2 - The semiconductor industry is approaching physical limits of Moore's Law, with the pace of process miniaturization slowing down, which may challenge Taiwan's leading position in wafer foundry and packaging [3] - Advanced packaging technologies like CoWoS and InFO are becoming essential for improving chip integration efficiency, shifting the focus from merely cost control to performance enhancement [3] - System design is emphasized as a crucial area for future focus, as it will ultimately dictate the direction of industry development [3]

Core Viewpoint - The article discusses the upcoming Heterogeneous Integration Annual Conference organized by TrendBank and the Yongjiang Laboratory, focusing on the strategic opportunities in the new generation of chip development, particularly in heterogeneous integration technology [10][11]. Conference Overview - The conference will take place from November 17-19, 2025, at the Nanyuan Wanghai Hotel in Zhenhai District, Ningbo, with an expected attendance of 300-500 participants [11]. - The theme of the conference is "Focusing on the Frontier of Heterogeneous Integration Technology, Advancing the Journey of Advanced Packaging" [10][11]. Key Topics and Sessions - The conference will cover various advanced packaging technologies, including 2.5D/3D heterogeneous integration, optoelectronic co-packaging, wafer-level bonding, and glass-based packaging [11]. - Notable sessions will include discussions on the challenges and opportunities in heterogeneous integration technology, advanced packaging trends, and the impact of AI on semiconductor manufacturing [4][6][9]. Strategic Importance - Ningbo is highlighted as a core port city with a strong foundation in advanced manufacturing, making it an ideal location for this conference aimed at enhancing the electronic information industry in the Yangtze River Delta region [9][10]. - The Yongjiang Laboratory is recognized as a provincial-level laboratory approved by the Zhejiang provincial government, focusing on electronic information materials and micro-nano device preparation [9][11]. Participation and Registration - The conference offers various ticket options, including early bird discounts for registrations completed by October 31, 2025 [13]. - Participants will have access to conference materials, lunch, and a banquet on November 18 [13].