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AMD,盯上了互联
半导体芯闻· 2025-09-29 09:45
Core Insights - AMD is planning significant improvements in its Zen 6 processors through the implementation of D2D (die-to-die) interconnect technology, which has already been observed in the Strix Halo APU [1][4] - The current D2D communication method relies on SERDES PHYs, which convert parallel data streams into serial bit streams, leading to inefficiencies in energy consumption and increased latency [3][6] - The Strix Halo APU introduces a new communication method that utilizes TSMC's InFO-oS and a re-distribution layer (RDL) to enhance bandwidth and reduce power consumption and latency [5][7] Existing Interconnect Mechanism - AMD employs SERDES PHYs at the edges of CCDs for die-to-die communication, allowing high-speed serial channels to communicate across organic substrates [3] - The SERDES method incurs overhead due to serialization/deserialization processes, consuming energy and adding latency to D2D communication [3] New Method in Strix Halo - The Strix Halo APU features a redesigned communication approach for Zen 6 chiplets, utilizing short parallel wires in the RDL to eliminate the overhead associated with data flow conversion [5] - High Yield discovered a rectangular array of small solder pads in Strix Halo, indicating the implementation of Fan-Out technology and the removal of large SERDES modules [5] Improvements and Challenges of the New Method - The new Fan-Out method reduces power and latency requirements by eliminating the need for serialization/deserialization, while overall bandwidth can be increased by adding more ports on the CPU Fabric [7] - However, the complexity of multi-layer RDL design increases the difficulty of implementation, and the space occupied by Fan-Out wiring necessitates adjustments in wiring priorities [7]
英伟达下一代GPU,巨幅升级!
半导体芯闻· 2025-09-29 09:45
Core Insights - NVIDIA and AMD are competing to develop superior AI architectures, with significant upgrades planned for their next-generation products in terms of power consumption, memory bandwidth, and process node utilization [1][2] - AMD's Instinct MI450 AI series is expected to be highly competitive against NVIDIA's Vera Rubin, with both companies making substantial modifications to their designs [1][5] Group 1: AMD's Optimism and Product Comparison - AMD executive Forrest Norrod expressed optimism about the MI450 product line, likening it to AMD's transformative "Milan moment" with the EPYC 7003 series [2] - Norrod stated that MI450 will be more competitive than NVIDIA's Vera Rubin and will utilize AMD's technology stack [3] - The MI450X's TGP has increased by 200W, while Rubin's TGP has risen by 500W to 2300W, indicating a significant enhancement in performance [5] Group 2: Specifications and Technological Advancements - The MI450 is rumored to launch in 2026 with HBM4 memory, offering up to 432 GB per GPU and a memory bandwidth of approximately 19.6 TB/s, while Vera Rubin is expected to have around 288 GB per GPU and a bandwidth of ~20 TB/s [6] - AMD's dense compute performance is estimated at ~40 PFLOPS, compared to ~50 PFLOPS for NVIDIA's offering [6] - Both companies are expected to narrow the technological gap as they adopt similar technologies, including HBM4 and TSMC's N3P node [6] Group 3: D2D Interconnect Technology - AMD plans to significantly enhance its D2D interconnect technology with the upcoming Zen 6 processors, as evidenced by developments in the Strix Halo APU [7][8] - The current D2D communication method using SERDES has limitations in efficiency and latency, which AMD aims to address with new designs [10][12] - The Strix Halo utilizes TSMC's InFO-oS and redistribution layer (RDL) to improve communication between chips, reducing power consumption and latency [12][14]
下一代GPU,竞争激烈
半导体行业观察· 2025-09-29 01:37
Core Viewpoint - NVIDIA and AMD are competing to develop superior AI architectures, with significant upgrades planned for their next-generation products in terms of power consumption, memory bandwidth, and process node utilization [2][3]. Group 1: AI Product Competition - AMD's Instinct MI450 AI series is expected to compete fiercely with NVIDIA's Vera Rubin, with both companies making substantial modifications to their designs [2][5]. - AMD executive Forrest Norrod expressed optimism about the MI450 product line, likening it to AMD's transformative "Milan moment" with the EPYC 7003 series [3]. - The MI450 is projected to be more competitive than NVIDIA's Vera Rubin, with AMD planning to leverage its own technology stack for future products [3]. Group 2: Technical Specifications - The MI450X's Total Graphics Power (TGP) has increased by 200W, while the TGP for Rubin has risen by 500W to 2300W, indicating a response to market competition [5]. - Memory bandwidth for Rubin has improved from 13 TB/s to 20 TB/s per GPU, showcasing the enhancements made in both product lines [5]. - AMD's MI450 is rumored to feature HBM4 memory with up to 432 GB per GPU, while NVIDIA's Rubin is expected to have around 288 GB per GPU [6]. Group 3: Interconnect Technology - AMD plans to significantly enhance its chip-to-chip (D2D) interconnect technology with the upcoming Zen 6 processors, as evidenced by developments in the Strix Halo APU [8][10]. - The new D2D interconnect method reduces power consumption and latency by eliminating the need for serialization/deserialization, thus improving overall bandwidth [12][15]. - The Strix Halo's design utilizes TSMC's InFO-oS technology and redistribution layers (RDL) to facilitate efficient communication between chips [10][15].