股份發行人及根據《上市規則》第十九B章上市的香港預託證券發行人的證券變動月報表 截至月份: 2025年7月31日 狀態: 新提交 致：香港交易及結算所有限公司 公司名稱: 中國上城集團有限公司 呈交日期: 2025年8月5日 I. 法定/註冊股本變動 | 1. 股份分類 | 普通股 | 股份類別 | 不適用 | | 於香港聯交所上市 (註1) | | 是 | | | --- | --- | --- | --- | --- | --- | --- | --- | --- | | 證券代號 (如上市) | 02330 | 說明 | | | | | | | | | | 法定/註冊股份數目 | | | 面值 | | 法定/註冊股本 | | | 上月底結存 | | | 30,000,000,000 | HKD | | 0.01 HKD | | 300,000,000 | | 增加 / 減少 (-) | | | | | | HKD | | | | 本月底結存 | | | 30,000,000,000 | HKD | | 0.01 HKD | | 300,000,000 | 本月底法定/註冊股本總額： HKD 300,00 ...

Core Viewpoint - The article discusses the challenges and contradictions faced by the U.S. semiconductor industry, particularly in relation to the CHIPS Act and the role of TSMC, highlighting the internal chaos and global competition that the U.S. is experiencing in its pursuit of technological sovereignty [3][4]. Group 1: CHIPS Act and TSMC's Role - The CHIPS Act, initiated during the Biden administration, is now facing criticism and funding cuts from the Trump administration, revealing the complexities of U.S. technology policy [3]. - TSMC, as the largest foundry globally, is seen as a strategic asset for the U.S., receiving significant financial support for its investments in Arizona, including $6.6 billion in subsidies and $25 billion in tax incentives [3]. - Despite the financial incentives, TSMC's most advanced manufacturing processes (2nm and 1.4nm) will remain in Taiwan, indicating a strategic choice rather than a technical limitation [3]. Group 2: Global Competition and Subsidy Race - The U.S. has inadvertently sparked a global subsidy race, with major tech hubs investing over $150 billion in semiconductor manufacturing and R&D, raising concerns about potential overcapacity and profit compression [4]. - The original intent of the CHIPS Act was to reduce reliance on Asian supply chains and curb China's advancements in critical technologies, but the execution has led to a misalignment with these goals [4]. Group 3: Current Semiconductor Landscape - A 2022 survey by the U.S. Department of Commerce revealed that the most severe chip shortages were in traditional chips (40nm and above), which are primarily produced in Asia, indicating a disconnect between the CHIPS Act's objectives and the actual market needs [4]. - The political divide in the U.S. regarding semiconductor policy has led to uncertainty about the future of the CHIPS Act, with potential delays or renegotiations of subsidies, causing semiconductor companies to adopt a wait-and-see approach [4]. Group 4: Future Directions - The establishment of the National Semiconductor Technology Center (NSTC) in New York marks a new phase for U.S. semiconductor policy, focusing on advanced research in 1.4nm and quantum chips [5]. - Success in regaining technological leadership will require not only financial investment but also clear strategy and international coordination to avoid misdirection and execution imbalances [5].

Core Viewpoint - The article highlights the recognition of Dr. C.C. Wei and Dr. Mark Liu, leaders of TSMC, as the joint recipients of the 2025 Robert N. Noyce Award for their significant contributions to the semiconductor industry [2][4]. Group 1: Award Announcement - The Semiconductor Industry Association (SIA) announced that Dr. C.C. Wei and Dr. Mark Liu will receive the Robert N. Noyce Award in 2025 [2]. - The award ceremony will take place on November 20, 2025, in San Jose, California [2]. Group 2: Contributions to the Industry - Dr. Wei and Dr. Liu are recognized for reshaping the modern semiconductor ecosystem and revolutionizing chip manufacturing technology [4]. - Under their leadership, TSMC has become the largest chip foundry globally and a cornerstone of the semiconductor supply chain [4]. - TSMC has developed numerous groundbreaking technologies that have transformed computing performance, energy efficiency, and the global supply chain [4]. Group 3: Leadership Background - Dr. C.C. Wei has held various leadership roles at TSMC since joining in 1998, including CEO and President [5]. - Dr. Mark Liu has also served in multiple executive positions at TSMC, contributing to its growth and innovation [6]. - Both leaders emphasize the collective effort of their teams and the importance of innovation in the semiconductor field [5][6].

Core Insights - The demand for logic-to-memory integration driven by AI and high-performance computing is propelling advancements in panel-level packaging (PLP), with expectations that PLP will approach 10 times the maximum reticle size in the coming years [2][3] - Fan-out panel-level packaging (FOPLP) is emerging as a cost-effective solution, replacing silicon interposers with organic interposers, which is crucial for accommodating larger chip sizes and higher I/O counts [2][3][20] - The panel-level packaging market is projected to grow significantly, from $160 million in 2024 to $650 million, and nearly tripling to approximately $2.2 billion by 2030 [4] Panel-Level Packaging Developments - The integration of organic interposers and glass substrates is advancing, with companies like TSMC transitioning from wafer-based to panel-based processes for advanced packaging [3][4] - The choice of panel size varies based on application needs, with sizes ranging from 310 x 310 mm to 700 x 700 mm, influenced by existing manufacturing capabilities [5][6] - The utilization efficiency of panel-level packaging improves with larger interposer sizes, significantly reducing waste compared to wafer-level processes [6][10] Manufacturing Techniques and Challenges - Various manufacturing processes are being implemented in fan-out packaging, including chip-first, RDL-first, and mold-first methods, each with its own advantages and challenges [12][14] - Warpage remains a critical issue in fan-out packaging, exacerbated by differences in thermal expansion coefficients between materials, necessitating new materials and process controls to mitigate this risk [16][18][20] - Laser direct imaging and step-and-repeat lithography are both utilized for RDL patterning, with step-and-repeat lithography being more suitable for high throughput [10][20] Future Outlook - The future of panel-level packaging is promising, particularly for AI and HPC devices, as manufacturers seek to achieve yield rates comparable to current fan-out wafer-level packaging processes [20] - The development of new interlayer dielectric materials and molding materials with thermal expansion coefficients closer to silicon will enhance control over chip displacement and warpage [20]

Core Viewpoint - The article focuses on the latest advancements in semiconductor technology presented at the VLSI conference, highlighting innovations in chip manufacturing, including digital twins, advanced logic transistors, and future interconnects, as well as comparisons between Intel's 18A process and TSMC's technologies [1]. Group 1: FlipFET Design - Despite various restrictions, China continues to advance in semiconductor R&D, with Peking University's FlipFET design gaining significant attention for its novel patterning scheme that achieves PPA similar to CFET without the challenges of monolithic or sequential integration [2]. - The FlipFET technology involves a process where NMOS is formed on the front side and PMOS on the back side of the wafer, showcasing good performance for both types of transistors [8][10]. - The main drawback of FlipFET is its cost, as it requires multiple back-end processes and is more susceptible to wafer warping and alignment errors, potentially affecting yield [12]. Group 2: DRAM Developments - DRAM is at a pivotal point in its five-year roadmap with two key advancements: 4F2 and 3D technologies, with 4F2 expected to increase density by 30% compared to 6F2 without reducing minimum feature size [16][23]. - The 4F2 architecture necessitates vertical channel transistors to fit within the unit size, presenting manufacturing challenges due to high aspect ratios [24][31]. - 3D DRAM is being developed concurrently, with Chinese manufacturers showing strong motivation to innovate in this area due to its independence from advanced lithography technologies [36]. Group 3: Digital Twin Technology - Digital twin technology is becoming essential in semiconductor design and manufacturing, allowing for design exploration and optimization in a virtual environment before physical production [79]. - This technology spans atomic-level simulations to wafer-level optimizations, enhancing productivity and yield in semiconductor fabrication [80][87]. - The implementation of "unmanned" fabs is a future goal, aiming for automated maintenance and operation without human intervention, which poses challenges in standardizing processes across different equipment vendors [92]. Group 4: Intel's 18A Process - Intel's 18A process, set to enter mass production in late 2025, combines Gate-All-Around transistors with a PowerVia back power network, significantly reducing interconnect spacing and improving yield [74][78]. - The 18A process claims a 30% reduction in SRAM size compared to Intel's 3rd generation baseline, with performance improvements of approximately 15% at the same power consumption [76]. - The process also features a reduction in the number of front metal layers and an increase in back metal layers to support the new architecture, indicating a shift towards more efficient manufacturing [77].

Core Viewpoint - The article highlights the rising prominence of Gallium Nitride (GaN) technology in various sectors, particularly in data centers and automotive applications, while Silicon Carbide (SiC) faces challenges. The power GaN market is projected to grow significantly, with a forecasted compound annual growth rate (CAGR) of 41% from 2023 to 2029, reaching over $2 billion [1]. Group 1: GaN Market Dynamics - NVIDIA is leading the transition to 800 V HVDC data center power infrastructure, which will significantly utilize GaN technology [1]. - Yole Group predicts that the power GaN market will grow tenfold from 2023 to 2029, driven by its higher switching frequency and power density, as well as reduced energy loss [1]. Group 2: TSMC's Shift in GaN Production - TSMC announced it will cease GaN foundry production by July 2027, citing low profit margins and a shift in focus towards advanced logic processes [6]. - This decision has forced existing customers to seek new partnerships, indicating a significant shift in the GaN foundry landscape [6]. Group 3: GaN Production Challenges and Opportunities - InnoScience, a leading domestic GaN manufacturer, emphasizes the importance of 8-inch wafer production for cost-effectiveness and scalability, arguing that 6-inch production is not viable for large-scale applications [7]. - The transition to 12-inch GaN production is seen as feasible but requires significant preparation and experience from 8-inch production [10][12]. Group 4: GaN Applications Beyond Consumer Electronics - GaN technology is not limited to consumer electronics; it has potential applications in electric vehicles (EVs) and data centers, with partnerships like that with CATL showcasing its capabilities [15][17]. - The article discusses the potential for GaN in smart and electric vehicles, highlighting its role in energy management and as part of distributed energy systems [16]. Group 5: Strategic Collaborations - InnoScience's collaboration with STMicroelectronics aims to enhance GaN power solutions across various sectors, leveraging each company's strengths to improve supply chain resilience [18]. - The partnership is expected to expand GaN product offerings and market capabilities, indicating a strategic move to solidify positions in the growing GaN market [18].

Core Viewpoint - TSMC's expansion into multiple continents poses challenges to its strategic bandwidth and investor patience, despite its status as a leading semiconductor manufacturer [1] Group 1: U.S. Expansion Costs - TSMC's commitment to a $165 billion investment in the U.S. includes plans to build three chip factories, with a notable facility in Arizona expected to produce chips using advanced 2nm technology by 2028 [2] - The timeline for U.S. production is several years behind Taiwan's, indicating that U.S. tech companies may still need to import advanced chips from Taiwan for the foreseeable future [2] - TSMC's international ambitions are facing setbacks, with a $20 billion factory in Kumamoto, Japan, experiencing delays as resources are reallocated to the U.S. market [2] Group 2: Strategic Tug-of-War - Recent legislation in Taiwan aims to retain advanced manufacturing capabilities domestically, ensuring that TSMC's overseas factories lag behind its local fabs by at least one generation [3] - This policy enhances Taiwan's strategic advantage but limits the role of U.S. or Japanese factories in producing cutting-edge chips [3] - TSMC's global expansion may not fully alleviate Western concerns about semiconductor dependency, as the company remains geographically tied to Taiwan [3] Group 3: Execution Risks - Investors are concerned about TSMC's ability to manage multiple billion-dollar chip projects across regions with varying regulatory, political, and logistical challenges, which could lead to execution risks and underutilization of capacity [4] - TSMC asserts that its plans are driven by customer demand and strategic opportunities, claiming that investments in the U.S. will not detract from expansion in other regions [4] Group 4: Uncertainty from Tariffs - The semiconductor sector has not yet been impacted by tariffs from the Trump era, but the U.S. Department of Commerce is investigating whether to impose national security-related tariffs on imported chips, adding another layer of unpredictability [5] Group 5: Implications for TSMC Shareholders - TSMC's stock fell by 0.5% in Taipei, reflecting the complexity of its future development amid geopolitical challenges [6] - Investors must weigh the benefits of geopolitical hedging against the execution risks of building complex manufacturing capabilities in multiple regions [6] - TSMC remains essential to global technology but must demonstrate its ability to be indispensable across various locations simultaneously [6]

Core Viewpoint - The article discusses the significant upgrade in data center power infrastructure driven by the increasing demand for AI computing power, particularly focusing on NVIDIA's 800V High Voltage Direct Current (HVDC) technology, which is expected to reshape the third-generation semiconductor foundry landscape by 2027 [1][2]. Group 1: HVDC Technology and Market Dynamics - NVIDIA's 800V HVDC technology allows for an 85% increase in power transmission through the same size of wire compared to traditional architectures, with a key difference being the conversion of 800V DC to 54V DC [1]. - The demand for Power ICs in Compute Trays is expected to rise, with memory voltage needing to shift from 54V to 12V, creating opportunities for Taiwanese companies like Dazhong (8081) and Maida (6138) to capture market share [2]. - The collaboration between NVIDIA and Navitas involves the use of GaN and SiC technologies; however, TSMC's decision to gradually exit the GaN market raises questions about the future application of GaN in data centers due to safety concerns [2]. Group 2: Semiconductor Industry Implications - TSMC is optimizing its production capacity by reallocating workforce from older plants to support advanced packaging, which may create opportunities for other foundries like Lijidian to fill the gap in certain mature and specialized process nodes [2]. - The semiconductor industry is expected to see overseas PMIC manufacturers adjust their product offerings based on customer needs, providing Taiwanese supply chains with opportunities to penetrate Tier 1 customers [3].

Core Viewpoint - TSMC plans to exit the gallium nitride (GaN) business within two years [1] Group 1 - TSMC's decision indicates a strategic shift away from the GaN market [1] - The exit from the GaN business may impact TSMC's product offerings and market positioning [1] - This move reflects broader trends in the semiconductor industry regarding material focus and technology investments [1]

Core Viewpoint - Intel's new CEO, Pat Gelsinger, is considering a significant shift in its wafer foundry strategy to attract major clients, potentially prioritizing the development of the next-generation 14A process over the previously planned Intel 18A process [1][2]. Group 1: Strategy and Development - Intel may halt marketing the 18A process to new clients as early as July, with a final decision possibly delayed until fall due to the complexity and financial implications involved [1]. - The company is currently in the risk production phase for the Intel 18A process, which is expected to reach mass production this year, but there are indications that resources may be redirected towards the 14A process [1][2]. - The 14A process is viewed as having the potential to surpass TSMC's technology in certain aspects, aiming to attract major clients like Apple and Nvidia, who currently rely on TSMC for their chip production [1]. Group 2: Financial Implications - If Intel decides to abandon the 18A and 18A-P processes, it may incur significant write-downs, potentially amounting to hundreds of millions or even billions of dollars [2]. - Intel's primary customers for the 18A process have been internal, with plans to produce the Panther Lake laptop chips, which are touted as the most advanced processors designed and manufactured in the U.S. [2]. Group 3: Client Commitments and Market Position - Intel has made commitments to Amazon and Microsoft to produce a limited quantity of chips using the 18A process, with set delivery timelines [2][3]. - TSMC has highlighted its advancements in 2nm and A16 process technologies, indicating a competitive edge in energy-efficient computing, with most innovators collaborating with TSMC [3].