Core Viewpoint - Intel Foundry has showcased its advanced front-end and back-end process solutions for AI and high-performance computing (HPC) applications, highlighting a "AI chip test vehicle" that demonstrates the company's packaging technology capabilities [1][2]. Group 1: AI Chip Test Vehicle - The showcased AI chip test vehicle is not a functioning AI accelerator but serves to validate the physical assembly of future AI and HPC processors, demonstrating a complete integration solution [2]. - The test vehicle integrates four logic chip blocks, 12 high-bandwidth memory (HBM4) stacks, and two I/O chip blocks, with a production capability that distinguishes it from previous concept products [1][2]. Group 2: Technology and Architecture - The core of the technology platform consists of four large logic chip blocks built on Intel's 18A process technology, featuring RibbonFET and PowerVia technologies [3]. - Enhanced embedded multi-chip interconnect bridge technology (EMIB-T) is utilized for interconnecting components, with upgraded features to maximize interconnect density and power efficiency [3]. - The platform supports Universal Chiplet Interconnect Express (UCIe) standards, enabling data transfer rates of 32 Gbps and above, which is also compatible with the C-HBM4E stacks [3]. Group 3: Strategic Direction - Intel's roadmap includes a dedicated 18A-PT process technology for chiplet stacking, which incorporates back power delivery and through-silicon vias (TSVs) [4]. - The AI chip test vehicle employs Foveros packaging technologies to achieve high-precision copper-copper bonding, facilitating a mixed integration architecture that combines horizontal and vertical connections [4]. Group 4: Power Supply Innovations - The technology platform integrates several power delivery innovations, including PowerVia, Omni MIM capacitors, and embedded decoupling capacitors, aimed at addressing power supply challenges in multi-chip architectures [5]. - The design of a layered power network is intended to provide stable and clean power during peak computational demands, particularly for generative AI workloads [6]. Group 5: Future Prospects - The introduction of the AI chip test vehicle is a strategic move by Intel to attract customers, with the potential for the upcoming AI accelerator, codenamed Jaguar Shores, to adopt the showcased technology architecture by 2027 still under consideration [6].

公众号记得加星标⭐️，第一时间看推送不会错过。 这一封装方案与台积电目前的技术路线存在显著差异（后文将进一步阐述）。简言之，该技术概念印 证了一个趋势 —— 下一代高性能人工智能处理器将采用多芯片粒架构，而英特尔代工事业部已具备 相应的制造能力。 （来源： tomshardware ） 该技术平台的核心是 4 个大型逻辑芯片块，据称基于英特尔 18A 制程工艺打造，因此集成了环绕栅 极晶体管（RibbonFET）与背面供电技术（PowerVia）。逻辑芯片块两侧配置类 HBM4 内存堆栈与 I/O 芯片块，各组件间预计通过直接嵌入封装基板的增强型嵌入式多芯片互连桥接技术 2.5D 桥接器 （EMIB-T）实现互联。英特尔对 EMIB-T 技术进行了升级，在桥接器内部增设硅通孔（TSV），使 电力与信号既能横向传输，也可纵向流通，从而最大限度提升互连密度与供电效率。从逻辑架构来 看，该平台针对通用芯片互连标准（UCIe）的芯粒间接口设计，支持 32 吉比特每秒（GT/s）及以 上的传输速率，这一接口标准似乎也被用于连接类相干高带宽内存 4 增强版（C-HBM4E）堆栈。 这款测试载体还提前披露了英特尔向垂直整合 ...