Core Viewpoint - TSMC plans to build four advanced packaging (AP) factories to address capacity shortages and maintain its competitive edge in the semiconductor industry, particularly in advanced packaging technologies like CoWoS [1][4][11] Group 1: TSMC's Expansion Plans - TSMC will announce the expansion of four advanced packaging factories in Tainan, including locations in Chiayi Science Park and Southern Science Park [1] - The company aims to start mass production at its AP factory 1 in the Ziyi Technology Park in the first half of this year [1] - TSMC's expansion is a response to concerns about its potential transformation into "American TSMC" due to recent factory expansions in the U.S. [1] Group 2: Industry Trends and Challenges - The global tech industry is facing intense competition for advanced packaging technology, particularly TSMC's CoWoS, which is critical for connecting high-performance chips with ultra-fast memory [4][9] - By 2026, the bottleneck in AI GPU supply will shift from chip shortages to the complex assembly processes required for advanced packaging [4][9] - The transition from wafer-level packaging (WLP) to fan-out panel-level packaging (FOPLP) is expected to increase processing capacity significantly [11] Group 3: Strategic Implications - NVIDIA has secured nearly 60% of TSMC's CoWoS capacity for 2026, influencing competitors like AMD and Broadcom to vie for the remaining capacity [7] - The advanced packaging secondary market is rapidly maturing, with companies like Intel positioning their packaging technologies as alternatives to TSMC [8] - The industry's reliance on TSMC for advanced packaging creates vulnerabilities, as geopolitical stability in the Taiwan Strait remains a critical factor for the global AI economy [8][12] Group 4: Future Outlook - The industry's focus is shifting towards the physical realities of AI hardware, with advanced packaging becoming a crucial factor in the growth of AI capabilities [9][10] - Upcoming challenges include the transition to glass substrates for improved interconnect density and thermal management, which could disrupt TSMC's current dominance [11] - The success of HBM4 chip yields and the ramp-up of TSMC's AP7 capacity will be closely monitored, as delays could impact the release of next-generation AI models [12]

Core Viewpoint - The demand for semiconductor packaging is increasing due to the rise of artificial intelligence, leading companies to shift towards Fan-Out Panel Level Packaging (FOPLP) for better efficiency and cost reduction [1][2]. Group 1: Industry Developments - Taiwan's panel manufacturer Innolux plans to start mass production of FOPLP in the first half of 2025, aiming to surpass competitors like TSMC and ASE [1][2]. - ASE has invested $200 million to develop large-size FOPLP technology, expanding substrate size from 300mm x 300mm to 600mm x 600mm, with equipment expected to arrive in Q2 and trial production in Q3 [2]. - TSMC is focusing on micro FOPLP production lines, with expectations to achieve results within three years, favoring a 300mm x 300mm size over the rumored 515mm x 510mm [2]. Group 2: Technical Advantages - Current CoWoS packaging technology uses circular substrates, which limit chip placement as size increases. In contrast, FOPLP utilizes rectangular substrates, allowing for more chips per panel, thus improving utilization and reducing costs [2].