公众号记得加星标⭐️，第一时间看推送不会错过。 2013年，台积电斥资100亿美元押注苹果公司。张忠谋承诺在苹果公司投入巨资建设20纳米制程，尽 管当时经济效益尚不明朗，但他相信苹果会填满这些晶圆厂。"我把公司都押上了，但我没想到会 输，"张忠谋后来回忆道。事实证明他是对的。苹果A8芯片于2014年发布，台积电从此一帆风顺。 苹果公司在台积电的年度支出从2014年的20亿美元增长到2025年的240亿美元，12年间增长了12 倍。苹果公司在台积电营收中的占比也从9%飙升至峰值的25%，并在2025年稳定在20%。更引人注 目的是苹果公司在制程节点发布方面的统治地位：自20纳米制程以来，其占比始终保持在50%以上， 在某些情况下甚至接近100%。实际上，自20纳米制程以来，苹果公司为每一次主要制程节点的良率 提升都提供了资金支持。 如今，代工模式占据主导地位。集成器件制造商（IDM）仅靠单一客户难以支撑工艺开发和晶圆厂建 设支出。但即便如此，代工厂也需要一个需求量大、资金雄厚的"首选"客户来支持其持续发展。过去 十年，苹果一直是台积电的这样的客户。双方的强强联合将两家公司推向了新的高度，令竞争对手望 尘莫及，并 ...

公众号记得加星标⭐️，第一时间看推送不会错过。 2025年底，台积电刚刚完成了2纳米环栅（GAA）晶体管的架构革新——这是自2011年FinFET 问世以来晶体管结构最重大的变革。我们对此里程碑事件进行了广泛报道，实至名归。每片晶 圆的生产设备密集度将增加30%至50% ，这将推动一个持续多年的资本支出周期，SEMI预测到 2027年，该周期将达到1560亿美元。 相关报道指出，台积电表示，2 纳米技术已如期于2025 年第四季开始量产。 N2 技术采用第一代纳 米片(Nanosheet) 电晶体技术，提供全制程节点的效能及功耗进步，并发展低阻值重置导线层与超高 效能金属层间电容以持续进行2 纳米制程技术效能提升。 台积电指出，N2 技术将成为业界在密度和能源效率上最为先进的半导体技术，N2 技术采用领先的 纳米片电晶体结构，将提供全制程节点的效能及功耗的进步，以满足节能运算日益增加的需求。 N2 及其衍生技术将因我们持续强化的策略，进一步扩大台积电的技术领先优势。 与3 纳米的N3E 制程相比，在相同功耗下台积电2 纳米速度增加10% 至15%；在相同速度下，功耗降 低25% 至30%，同时芯片密度增加大于 ...

Core Viewpoint - TSMC controls advanced CoWoS packaging capacity, which is crucial for determining which AI chip manufacturers can scale production, making it a key player in the explosive growth of the AI market [1][2]. Group 1: TSMC's Role in AI Development - TSMC's CoWoS capacity is becoming increasingly critical for the survival and growth of other chip manufacturers and designers, as advanced packaging technology has become a new industry bottleneck [1]. - The rapid development of AI since 2023 has created trillions of dollars in market value, but supply chain bottlenecks, particularly in advanced manufacturing, are limiting growth [1][3]. - TSMC is a key factor in determining the speed and scale of AI development, with its capacity expansion plans aiming to double advanced wafer capacity by 2028 [4]. Group 2: Impact on Competitors - Google has reduced its 2026 TPU production target from 4 million to 3 million units due to limited access to TSMC's CoWoS technology, while NVIDIA has secured over half of TSMC's CoWoS capacity until 2027 [3]. - The shortage of CoWoS capacity may intensify competition, prompting other manufacturers like Intel to fill the gap and compete with TSMC in the foundry services sector [4][5]. - Companies like Google and Apple are exploring alternative solutions, such as Intel's EMIB packaging technology and engaging with Samsung's factories to meet their needs [4].

公众号记得加星标⭐️，第一时间看推送不会错过。 《电子工程时报》 3月份报道称，英特尔晶圆代工封装与测试副总裁马克·加德纳表示，公司正在"努 力"缓解先进封装芯片短缺的局面。加德纳指出，造成这种短缺的主要原因是客户依赖竞争对手（台 积电）的技术，并补充说，英特尔的优势在于其不受产能限制。值得注意的是，该报道暗示，AWS 和台湾的联发科等芯片设计公司正在选择英特尔晶圆代工作为供应商。 TrendForce指出，人工智能和高性能计算数据中心的蓬勃发展正推动着前所未有的需求，导致一家主 要先进封装供应商的供应出现瓶颈。这种供应紧张的局面正蔓延至竞争对手，迫使主要的芯片封装服 务提供商（CSP）寻求除CoWoS（芯片封装在晶圆基板上）之外的其他解决方案，而EMIB正逐渐成 为强有力的竞争者。 据报道，NVIDIA 和 AMD 正在评估英特尔晶圆代工的 14A 制程节点，而苹果和博通则在考虑采用 英特尔的 EMIB 封装技术来开发定制服务器加速器。香港广发证券指出，这些进展反映出顶级设计 公司越来越愿意重新考虑其前端工艺技术和后端封装的供应商。台积电等其他供应商的产能限制可能 是促使这些探索性举措的关键因素，封装的可用 ...

2025年进入尾声，年初刷屏的"半导体十大技术趋势预测"也到了交答卷的时刻。2nm、HBM4、先进封装、AI 处理器、智驾芯片、量子处理器等核心方 向，始终是行业关注重点。这一年来，这些预测的 "进度条" 究竟走了多少？今天一起顺着时间线，拆解十大方向的真实进展。 01 半导体十大预测，兑现几何？ | 十大预测 | 年初预测 | 达成进度 | | --- | --- | --- | | 2nm | 台积电、三星、英特尔均将在这一年里陆续推出自家的 | 台积电本季度晚些时候量产,三星、英特尔均已量产,但良 | | | 2nm或Intel 18A工艺制程。 | 率各异。 | | HBM4 | SK海力士、三星均计划今年实现量产。 | SK海力士HBM4已开始量产,第四季度开始出货。三星 | | | | HBM4大规模量产时间指向2026年。 | | 先进封装 | 台积电加速CoWoS产能扩充并扩大光罩尺寸;长电科技、 | 台积电CoWoS持续扩产,国内封测企业的工厂规划也顺利进 | | | 华天科技等一系列工厂建成投产。 | 行。 | | | 英特尔将推出Panther Lake和Clearwater Fores ...

Core Viewpoint - TSMC is considering advancing its chip production technology at its second factory in Japan to meet the demand for AI-related products, which may lead to construction delays and design changes [3][4]. Group 1: Factory Development - TSMC's second factory in Kumamoto, Japan, which began construction in late October, is now contemplating a shift to 4nm process technology, moving away from the initially planned 6nm and 7nm chips [3]. - The construction of the Kumamoto factory has reportedly been paused, with heavy machinery cleared from the site by early December [3]. - TSMC has informed suppliers that it will not add equipment to its existing factory in Kumamoto until at least 2026, as demand for 6nm and 7nm chips has decreased [4]. Group 2: Market Demand and Technology Shift - The demand for 6nm and 7nm chips has declined, impacting TSMC's production capacity utilization at its main facility in Taichung, Taiwan [4]. - TSMC has a history of adjusting its construction plans based on market demand, as seen with its facility in Kaohsiung, which shifted from mature processes to advanced 2nm technology [4]. - TSMC is also considering introducing advanced chip packaging technology in Japan, which is crucial for AI chip manufacturing [5]. Group 3: Partnerships and Support - TSMC's projects in Japan are supported by companies such as Sony Semiconductor Solutions, Denso, and Toyota [5].

Group 1 - The semiconductor revenue share is continuously increasing, with rapid growth in orders. The first 12-inch silicon carbide (SiC) substrate pilot line has been successfully commissioned, marking a significant advancement in domestic technology and production capabilities [1] - SiC's high thermal conductivity and processing window are expected to significantly enhance the cooling of CoWoS structures while reducing package size. SiC serves as an ideal material for high-performance CoWoS interlayers due to its thermal conductivity of 490 W/m·K, which is 2-3 times higher than that of silicon [2] - SiC's high refractive index and thermal conductivity make it an ideal substrate material for AR glasses. A single-layer SiC lens can achieve a field of view (FOV) of over 80 degrees, providing a thinner design and clearer visual effects [3] Group 2 - SiC's high hardness and thermal stability support the introduction of etching processes, effectively improving production capacity and yield. The company is actively expanding its 6 and 8-inch substrate capacity and has achieved breakthroughs in 12-inch SiC crystal growth technology [4] - The company maintains its profit forecast for 2025-2027, estimating net profits of 1 billion, 1.2 billion, and 1.5 billion yuan, corresponding to current P/E ratios of 58, 47, and 38 times, respectively, and maintains a "buy" rating [4]

Group 1 - The rapid development of AI chips is driving new demand for testing and packaging equipment, particularly for high-performance testing machines and advanced packaging technologies [2][4][38] - The semiconductor testing equipment market is expected to exceed $13.8 billion by 2025, with SoC and storage testing machines accounting for approximately $4.8 billion and $2.4 billion, respectively [3][50] - The complexity of SoC and advanced storage chips is increasing, leading to a significant rise in demand for high-performance testing machines [35][33] Group 2 - The demand for SoC testing machines is increasing due to the high integration and stability requirements of AI HPC chips, which significantly raise testing volume and time [3][50] - The storage testing machines are facing increased complexity due to HBM testing, which includes wafer-level testing and KGSD testing, replacing conventional packaging-level testing [3][44] - The core barriers in testing machines are the testing boards and chips, with a significant market share held by companies like Advantest and Teradyne, which dominate approximately 90% of the global semiconductor testing machine market [3][50] Group 3 - Advanced packaging technologies, such as HBM and CoWoS, are becoming mainstream, driving the demand for advanced packaging equipment [38][36] - The main difference between advanced and traditional packaging lies in the connection methods between chips and external electronics, with advanced packaging requiring more sophisticated equipment [4][38] - The investment suggestion highlights the potential opportunities in domestic testing and packaging equipment driven by AI chip advancements [4][5] Group 4 - The AI chip market in China is projected to reach approximately 140.6 billion yuan by 2024, with a compound annual growth rate (CAGR) of 36% from 2019 to 2024 [12][10] - The smart computing scale in China is expected to reach 640.7 EFLOPS by 2024, indicating a significant increase in demand for AI chips [12][10] - The end-side AI applications are rapidly expanding, leading to increased demand for SoC chips, which are expected to grow significantly in the market [27][25] Group 5 - The global SoC chip market is anticipated to reach $274.1 billion by 2030, driven by the increasing integration and performance requirements of AI applications [27][26] - SoC chips are essential for various applications, including mobile devices, smart home systems, and industrial control systems, highlighting their versatility [27][24] - The core of SoC chips lies in the IP cores, which are critical for achieving high integration, performance, and low power consumption [30][29] Group 6 - The majority of the AI chip market is still dominated by foreign giants, with domestic companies like Huawei, Haiguang, and Cambricon making strides to break the monopoly [32][31] - The performance of domestic AI chips is improving, with Huawei's Ascend series and Haiguang's DCU chips showing competitive capabilities against leading foreign products [32][31] - The ongoing trend of domestic substitution in the AI chip market is expected to accelerate as local companies enhance their technological capabilities [32][31]

Investment Rating - The report maintains a positive outlook on the semiconductor equipment industry, particularly driven by the rapid development of AI chips and the resulting demand for advanced testing and packaging equipment. Core Insights - The rapid development of AI chips is creating new demands for packaging and testing equipment, particularly for SoC and advanced storage chips, which are becoming increasingly complex and require high-performance testing machines [2][4]. - The semiconductor testing equipment market is projected to exceed $13.8 billion by 2025, with SoC and storage testing machines expected to account for approximately $4.8 billion and $2.4 billion, respectively [2][57]. - The report emphasizes the importance of domestic testing machine manufacturers, particularly in the context of rising AI testing requirements and the anticipated growth in the semiconductor testing equipment market [2][9]. Summary by Sections 1. AI Chip Development and Equipment Demand - The growth of AI chips is driving new requirements for testing and packaging equipment, particularly for SoC and advanced storage chips, which are becoming more complex [2][4]. - The demand for high-performance testing machines is significantly increasing due to the complexity of AI chips and advanced storage chips [2][9]. 2. Post-Process Testing - The report highlights the increasing requirements for AI testing and the focus on domestic testing machine leaders, predicting a market space for semiconductor testing equipment to exceed $13.8 billion by 2025 [2][57]. - The core barriers in testing machines are identified as the testing boards and chips, with a significant market share held by companies like Advantest and Teradyne [2][9]. 3. Post-Process Packaging - The report notes the rapid development of advanced packaging technologies, such as HBM and CoWoS, which are driving the demand for advanced packaging equipment [2][41]. - The distinction between traditional and advanced packaging processes is highlighted, with advanced packaging requiring additional graphic processing equipment [2][41]. 4. Investment Recommendations - Investors are advised to focus on domestic opportunities arising from AI chip development, particularly in testing and packaging equipment sectors [2][9]. - Specific companies mentioned for potential investment include Huafeng Measurement and Control, Changchuan Technology, and others involved in advanced packaging and testing equipment [2][9]. 5. Market Trends - The report indicates that the global SoC chip market is expected to reach $274.1 billion by 2030, driven by the increasing integration of AI applications in various devices [2][25]. - The demand for advanced storage solutions is also expected to rise, with AI servers requiring significantly higher DRAM capacities compared to traditional servers [2][20].

Core Viewpoint - Morgan Stanley reports that Nvidia is exploring a revolutionary chip packaging technology called CoWoP (Chip-on-Wafer-on-PCB), which is expected to replace the existing CoWoS packaging solution [2][3]. Group 1: CoWoP Technology Analysis - CoWoP utilizes advanced high-density PCB technology, eliminating the ABF substrate layer found in CoWoS packaging, and directly connecting the intermediary layer to the PCB [4]. - The potential advantages of CoWoP include simplified system structure, improved thermal management, lower power consumption, reduced substrate costs, and potential reduction in backend testing steps [10]. Group 2: Supply Chain Impact - The introduction of CoWoP is seen as negative news for ABF substrate manufacturers, as the added value of substrates may significantly decrease or disappear [8]. - Conversely, PCB manufacturers are presented with significant opportunities, particularly those with advanced mSAP capabilities and deep knowledge of substrate/packaging processes [8]. Group 3: Commercialization Challenges - Morgan Stanley analysts believe that the commercialization probability of CoWoP in the medium term is low due to multiple technical challenges [3][9]. - Current PCB technologies, even with mSAP, can only achieve line/space widths of 20-30 microns, which is still far from the desired performance levels [11]. Group 4: Nvidia's Innovation Leadership - Regardless of the success of CoWoP, Nvidia continues to lead innovations in data center AI infrastructure through a system-level approach [12]. - Nvidia's ongoing innovation capabilities are expected to maintain its leading position in the GPU sector and dominate competition with ASICs in the coming years [12].