同时，SiC 材料的高硬度和热稳定性亦支持刻蚀工艺的引入，有效提升产能和良率。 晶盛积极扩产6&8 英寸衬底产能，已具备12 英寸能力。晶盛目前已经攻克12 英寸碳化硅晶体生长中的 温场不均、晶体开裂等核心难题，实现了12 英寸超大尺寸晶体生长的技术突破，成功长出12 英寸导电 型碳化硅晶体。 盈利预测与投资评级：我们维持公司2025-2027 年归母净利润预测为10/12/15 亿元，对应当前PE 为 58/47/38 倍，维持"买入"评级。 投资要点 半导体收入占比不断提升，订单快速增长。12 英寸碳化硅衬底加工中试线通线，可兼容导电&半绝缘 型。9 月26 日，首条12 英寸碳化硅衬底加工中试线在晶盛机电子公司浙江晶瑞SuperSiC 正式通线，至 此，浙江晶瑞SuperSiC 真正实现了从晶体生长、加工到检测环节的全线设备自主研发，100%国产化， 标志着晶盛在全球SiC衬底技术从并跑向领跑迈进，迈入高效智造新阶段。 SiC 凭借其高热导率和高工艺窗口，有望显著提升CoWoS 结构散热并降低封装尺寸。英伟达GPU 芯片 从H100 到B200 均采用CoWoS 封装（芯片-晶圆-基板）技术。CoWoS ...

点击 最 下方 关注《材料汇》 ， 点击"❤"和" "并分享 添加 小编微信 ，寻 志同道合 的你 正文 AI芯片快速发展，带来封测设备新需求。 (1)测试机： SoC芯片作为硬件设备的"大脑"，承担着AI运算控制等核心功能，对计算性能和能耗的要求极高，这使得芯片设计和制造的复杂性大幅增加，先进存储 芯片为AI算力芯片提供高带宽的数据存储和传输支持，其容量和带宽的不断提升也进一步增加了芯片的复杂性，因此 SoC芯片和先进存储芯片的复杂性提升共同推 动了对高性能测试机需求的显著增长 ； (2)封装设备： HBM显存的高带宽突破了加速卡的显存容量限制；COWOS封装技术作为一种2.5D技术，是GPU与HBM高速互联的关键支撑。 2.5D和3D封装技术需 要先进的封装设备的支撑，进一步推动了对先进封装设备的需求增长 。 后道测试：AI测试要求提升，关注国产测试机双龙头。 我们预估2025年半导体测试设备市场空间有望突破138亿美元，SoC与存储测试机分别合计达48/24亿美元。 (1)SoC测试机： AIHPC芯片的高集成度、高稳定性要求以及先进制程特性，导致测试量与测试时间显著增加，从而推动了对SoC测试机的需求 ...

Investment Rating - The report maintains a positive outlook on the semiconductor equipment industry, particularly driven by the rapid development of AI chips and the resulting demand for advanced testing and packaging equipment. Core Insights - The rapid development of AI chips is creating new demands for packaging and testing equipment, particularly for SoC and advanced storage chips, which are becoming increasingly complex and require high-performance testing machines [2][4]. - The semiconductor testing equipment market is projected to exceed $13.8 billion by 2025, with SoC and storage testing machines expected to account for approximately $4.8 billion and $2.4 billion, respectively [2][57]. - The report emphasizes the importance of domestic testing machine manufacturers, particularly in the context of rising AI testing requirements and the anticipated growth in the semiconductor testing equipment market [2][9]. Summary by Sections 1. AI Chip Development and Equipment Demand - The growth of AI chips is driving new requirements for testing and packaging equipment, particularly for SoC and advanced storage chips, which are becoming more complex [2][4]. - The demand for high-performance testing machines is significantly increasing due to the complexity of AI chips and advanced storage chips [2][9]. 2. Post-Process Testing - The report highlights the increasing requirements for AI testing and the focus on domestic testing machine leaders, predicting a market space for semiconductor testing equipment to exceed $13.8 billion by 2025 [2][57]. - The core barriers in testing machines are identified as the testing boards and chips, with a significant market share held by companies like Advantest and Teradyne [2][9]. 3. Post-Process Packaging - The report notes the rapid development of advanced packaging technologies, such as HBM and CoWoS, which are driving the demand for advanced packaging equipment [2][41]. - The distinction between traditional and advanced packaging processes is highlighted, with advanced packaging requiring additional graphic processing equipment [2][41]. 4. Investment Recommendations - Investors are advised to focus on domestic opportunities arising from AI chip development, particularly in testing and packaging equipment sectors [2][9]. - Specific companies mentioned for potential investment include Huafeng Measurement and Control, Changchuan Technology, and others involved in advanced packaging and testing equipment [2][9]. 5. Market Trends - The report indicates that the global SoC chip market is expected to reach $274.1 billion by 2030, driven by the increasing integration of AI applications in various devices [2][25]. - The demand for advanced storage solutions is also expected to rise, with AI servers requiring significantly higher DRAM capacities compared to traditional servers [2][20].

Core Viewpoint - Morgan Stanley reports that Nvidia is exploring a revolutionary chip packaging technology called CoWoP (Chip-on-Wafer-on-PCB), which is expected to replace the existing CoWoS packaging solution [2][3]. Group 1: CoWoP Technology Analysis - CoWoP utilizes advanced high-density PCB technology, eliminating the ABF substrate layer found in CoWoS packaging, and directly connecting the intermediary layer to the PCB [4]. - The potential advantages of CoWoP include simplified system structure, improved thermal management, lower power consumption, reduced substrate costs, and potential reduction in backend testing steps [10]. Group 2: Supply Chain Impact - The introduction of CoWoP is seen as negative news for ABF substrate manufacturers, as the added value of substrates may significantly decrease or disappear [8]. - Conversely, PCB manufacturers are presented with significant opportunities, particularly those with advanced mSAP capabilities and deep knowledge of substrate/packaging processes [8]. Group 3: Commercialization Challenges - Morgan Stanley analysts believe that the commercialization probability of CoWoP in the medium term is low due to multiple technical challenges [3][9]. - Current PCB technologies, even with mSAP, can only achieve line/space widths of 20-30 microns, which is still far from the desired performance levels [11]. Group 4: Nvidia's Innovation Leadership - Regardless of the success of CoWoP, Nvidia continues to lead innovations in data center AI infrastructure through a system-level approach [12]. - Nvidia's ongoing innovation capabilities are expected to maintain its leading position in the GPU sector and dominate competition with ASICs in the coming years [12].

Group 1 - The continuous demand for AI chips has significantly increased the need for High Bandwidth Memory (HBM), which relies heavily on CoWoS (Chip on Wafer on Substrate) packaging technology [1][3] - CoWoS technology, developed by TSMC, allows for efficient integration of multifunctional chips in a compact space, enhancing chip performance, particularly for AI chips [3][7] - TSMC's CoWoS technology is currently monopolizing the advanced AI chip packaging market, with a projected compound annual growth rate of 40% for the advanced packaging market in the coming years [7][10] Group 2 - TSMC plans to increase its CoWoS production capacity from 36,000 wafers per month in 2024 to 90,000 by the end of this year and aims for 130,000 by 2026 [8] - The core challenge in CoWoS technology lies in achieving high yield rates during the packaging process, which is crucial for minimizing losses in HBM and other devices [10][14] - Domestic companies are actively developing similar CoWoS packaging technologies, with key players including Shenghe Jingwei and Tongfu Microelectronics, both facing common industry challenges [18][19] Group 3 - Shenghe Jingwei is recognized as a leading player in advanced packaging in China, focusing on Chiplet packaging and achieving significant revenue growth, with a reported revenue of $270 million in 2022 [19] - Tongfu Microelectronics primarily serves the domestic market and has faced challenges in overseas collaborations, including a failed partnership with AMD for CoWoS packaging [20][21] - Other companies, such as Yongxi Electronics, are also entering the advanced packaging market, leveraging their existing 2.5D packaging technology to potentially expand into HBM packaging [22][23]

Core Viewpoint - The discussion highlights the transformative impact of artificial intelligence (AI) on society, scientific discovery, and the importance of foundational knowledge for the younger generation in adapting to the AI era [1][5][7]. Group 1: AI Development Trends - The next trend in AI development is its penetration into the physical world, transitioning from "perceptual AI" to "generative AI" and now to "reasoning AI," which can understand and generate information [2][3]. - The upcoming wave is "physical AI," which will be applied in robotics and other physical machines, enhancing human capabilities [3]. Group 2: China's Role in AI - China plays a significant role in AI development, with the highest number of research papers published globally. The country excels in open-source projects, which have a global impact [4]. - Open-source models like DeepSeek and Tongyi Qianwen are among the top in the world, benefiting various sectors such as healthcare and finance [4]. Group 3: AI's Impact on Scientific Discovery - AI is poised to revolutionize scientific discovery by enabling a deeper understanding of biological processes, which could lead to advancements in drug design and longevity [5]. - The ability to understand the structure and significance of biological entities through AI presents substantial opportunities [5]. Group 4: Future of Chip Technology - The future of chip technology involves the development of three-dimensional transistors and advanced packaging techniques, with significant innovations expected in silicon photonics [5]. - The transition from single chips to stacked and multi-chip designs is a key focus area for the next two decades [5]. Group 5: Advice for the Younger Generation - Young individuals are encouraged to master foundational skills such as mathematics, reasoning, logic, and programming to effectively interact with AI [6][7]. - Critical thinking is essential for evaluating AI-generated answers, and understanding first principles is crucial for problem-solving [7].

Core Viewpoint - The discussion highlights the transformative impact of artificial intelligence (AI) on society, scientific discovery, and the future of chip technology, emphasizing the importance of foundational knowledge for the younger generation in adapting to the AI era [3][5][9]. Group 1: AI Development and Trends - AI is evolving from "perceptual AI" to "generative AI," with capabilities now extending to understanding and generating information across different modalities [5]. - The next wave of AI development is expected to penetrate the physical world, leading to advancements in robotics and other physical machines [5]. - Huang emphasized the significance of "reasoning AI," which can understand and solve complex problems previously unencountered [5]. Group 2: China's Role in AI - Huang noted that China leads the world in the number of research papers published in AI, showcasing its significant contributions to open-source projects [6]. - Open-source models developed in China, such as DeepSeek and Tongyi Qianwen, are recognized as top-tier globally, benefiting various sectors including healthcare and finance [6]. Group 3: AI's Impact on Scientific Discovery - AI is poised to revolutionize scientific discovery by aiding in the understanding of biological structures and processes, which could lead to breakthroughs in drug design and longevity [7]. - Huang highlighted the potential of AI to interpret complex biological data, which could unlock significant opportunities in medicine [7]. Group 4: Future of Chip Technology - Huang discussed the future of chip technology, predicting a shift towards three-dimensional transistors and advanced packaging techniques, such as "CoWoS" [7]. - Innovations in silicon photonics are also anticipated, indicating a promising future for chip development [7]. Group 5: Advice for the Younger Generation - Huang advised young people to focus on mastering foundational skills such as mathematics, reasoning, logic, and programming to effectively engage with AI [9]. - He stressed the importance of critical thinking to evaluate AI-generated answers and to articulate problems clearly when interacting with AI [9].

Core Viewpoint - UBS maintains a "Buy" rating for TSMC and raises the target price from NT$1,180 to NT$1,200, highlighting the company's growth potential driven by capacity expansion, financial forecasts, and industry trends [1][5] Group 1: Capacity Expansion and Strategic Positioning - TSMC's annual capacity is projected to reach 36 million 8-inch equivalent wafers by the end of 2023, with a production network spanning Taiwan and overseas [1] - The company operates four 12-inch and four 8-inch fabs in Taiwan, along with a 12-inch fab and two 8-inch fabs in the U.S. and China, ensuring supply chain stability and geopolitical risk mitigation [1] Group 2: Financial Performance and Projections - UBS raises TSMC's 2025 revenue growth forecast from 25% to 29%, with capital expenditure expectations adjusted to a range of $40 billion to $42 billion, driven by surging cloud AI demand and advanced process capacity [2] - The gross margin is expected to remain high at 57.0%, close to the historical peak of 58.8% in the previous quarter, with long-term EPS growth rate estimates increased from 16% to 18% [2] Group 3: AI Demand and Packaging Technology - Despite a downward revision in smartphone and PC shipment forecasts, optimism remains for cloud AI chip demand, with TSMC's CoWoS packaging capacity expected to reach 70,000 pieces per month by the end of 2025 and 100,000 pieces by the end of 2026, a 30% increase from previous plans [3] - This expansion is anticipated to alleviate supply concerns for high-end AI chips and boost the revenue share from packaging services [3] Group 4: Profitability and Cost Management - TSMC is expected to maintain a gross margin of 55.5% to 56.5% from Q3 2025 to 2026, significantly above market consensus of 53% to 55%, due to strategic price adjustments and supply chain management [3] - Price increases for N5 and N3 wafers are planned, with mobile products seeing a 3%-5% increase and HPC products up by 10% [3] Group 5: Capital Expenditure Strategy - TSMC plans to increase capital expenditure for N2 process and overseas expansion, with external capital expenditure expected to reach $40 billion in 2025, a 5% increase from previous plans [4] - This strategy aims to reinforce TSMC's technological leadership and prepare for the restructuring of the global semiconductor supply chain [4] Group 6: Valuation and Investment Recommendation - UBS maintains a "Buy" rating for TSMC, raising the 12-month target price to NT$1,200 based on stronger AI demand and cost management capabilities [5] - The current stock price of NT$1,055 corresponds to a 2025 P/E ratio of only 22 times, significantly lower than its long-term growth expectations, making TSMC a compelling choice for investors seeking core assets in the semiconductor industry [5]

Core Viewpoint - The article discusses the evolution and significance of TSMC's CoWoS packaging technology, particularly in relation to NVIDIA's increasing reliance on CoWoS-L for its Blackwell architecture, highlighting the challenges and advancements in the semiconductor industry [1][2][5]. Group 1: TSMC and NVIDIA Collaboration - TSMC has become a crucial partner for NVIDIA, especially in the CoWoS packaging technology, with NVIDIA's CEO stating that they have no alternative to TSMC for this advanced technology [1]. - TSMC has reportedly surpassed ASE Group to become the largest player in the global packaging and testing market, driven by the demand for advanced packaging solutions [1]. Group 2: CoWoS Technology Evolution - NVIDIA plans to increase the use of CoWoS-L packaging for its upcoming Blackwell series products, transitioning from CoWoS-S to meet the high bandwidth requirements of its GPUs [2]. - The CoWoS technology faces challenges due to the increasing chip sizes, which limit the number of chips that can be placed on a 12-inch wafer, and the associated thermal management issues [5]. Group 3: Innovations and Challenges - TSMC is exploring the use of flux-free bonding technology to address issues related to flux residue that can affect chip reliability, with testing expected to be completed by the end of the year [6]. - The current interposer size in TSMC's CoWoS packaging is 80x80mm, with plans to introduce larger sizes by 2026 and 2027, which may enhance performance but also pose design challenges [8]. Group 4: Future Technologies - TSMC is betting on CoPoS technology, which replaces the traditional wafer with a panel, allowing for greater chip density and efficiency, with plans for mass production by 2029 [9][10]. - CoPoS is positioned as a potential alternative to CoWoS-L, offering advantages in signal integrity and power transmission, particularly for high-performance applications [11]. Group 5: Market Implications - The shift from circular wafers to square panels in CoPoS technology is expected to significantly enhance production capacity and cost efficiency, making it competitive in AI, 5G, and high-performance computing sectors [12]. - Despite the advantages, the transition to CoPoS requires substantial investment in materials and equipment, and overcoming technical challenges related to precision and yield will be critical for its success [13].

Core Viewpoint - The article discusses the significant rise of TSMC's CoWoS packaging technology, driven by the increasing demand for GPUs in the AI sector, particularly through its partnership with NVIDIA, which has deepened over time [1][3]. Group 1: CoWoS Technology and NVIDIA Partnership - NVIDIA has emphasized its reliance on TSMC for CoWoS technology, stating that it has no alternative partners in this area [1]. - TSMC has reportedly surpassed ASE Group to become the largest player in the global packaging market, benefiting from the growing demand for advanced packaging solutions [1]. - NVIDIA's upcoming Blackwell series will utilize more CoWoS-L packaging, indicating a shift in production focus from CoWoS-S to CoWoS-L to meet the high bandwidth requirements of its GPUs [3]. Group 2: Challenges and Innovations in CoWoS - The increasing size of AI chips poses challenges for CoWoS packaging, as larger chips reduce the number of chips that can fit on a 12-inch wafer [4]. - TSMC is facing difficulties with the use of flux in CoWoS, which is essential for chip bonding but becomes problematic as the size of the interposer increases [4][5]. - TSMC is exploring flux-free bonding technologies to improve yield rates and address the challenges posed by flux residue [5]. Group 3: Future Developments and Alternatives - TSMC plans to introduce CoWoS-L with a mask size of 5.5 times larger by 2026 and aims for a record 9.5 times larger version by 2027 [8]. - The company is also developing CoPoS technology, which replaces traditional wafers with panel substrates, allowing for higher chip density and efficiency [9][10]. - CoPoS is positioned as a potential alternative to CoWoS-L, targeting high-performance applications in AI and HPC systems [12]. Group 4: Technical Comparisons - FOPLP and CoPoS both utilize large panel substrates but differ in architecture; FOPLP does not use an interposer, while CoPoS does, enhancing signal integrity for high-performance chips [11]. - CoPoS is transitioning to glass substrates, which offer better performance characteristics compared to traditional organic substrates [12]. - The shift from round wafers to square panels in CoPoS aims to improve yield and reduce costs, making it more competitive in the AI and 5G markets [12]. Group 5: Challenges Ahead - Transitioning to square panel technology requires significant investment in materials and equipment, along with overcoming technical challenges related to pattern precision [14]. - The demand for finer RDL line widths poses additional challenges for suppliers, necessitating breakthroughs in RDL layout technology [14]. Conclusion - The future of TSMC's packaging technologies appears promising, with ongoing innovations and adaptations to meet the evolving demands of the semiconductor industry [14].