最近市场炒得火热的芯片晶圆板封装（CoWoP）技术，与现有的CoWoS封装有什么区别？对供应 链有何影响？商业化前景如何？ 8月5日，据追风交易台消息，摩根大通在最新研报中称，英伟达正在探索一项革命性的芯片封装 技术CoWoP（Chip-on-Wafer-on-PCB），该技术有望替代现有的CoWoS封装方案。 摩根大通指出，这一技术变革将利用先进的高密度PCB（印刷电路板）技术，去除CoWoS封装中 的ABF基板层，直接将中介层与PCB连接。 如果您希望可以时常见面，欢迎标星收藏哦~ 来源 ：内容来自 钜亨网 。 摩根大通称，英伟达正在探索的芯片封装技术CoWoP，将利用先进的高密度PCB（印刷电路板） 技术，去除CoWoS封装中的ABF基板层，直接将中介层与PCB连接，具有简化系统结构，更好的 热管理性能和更低功耗等优势。该技术有望替代现有的CoWoS封装方案。 该行还在研报中详细分析了"CoWoP"技术对于供应链的影响，认为对ABF基板厂商显然是负面消 息，却是PCB制造商的重大机遇。 虽然，摩根大通分析师认为该技术在中期内商业化机率较低，主要受制于多重技术挑战，但是该行 在研报中强调：无论CoWoP是 ...

Group 1 - The continuous demand for AI chips has significantly increased the need for High Bandwidth Memory (HBM), which relies heavily on CoWoS (Chip on Wafer on Substrate) packaging technology [1][3] - CoWoS technology, developed by TSMC, allows for efficient integration of multifunctional chips in a compact space, enhancing chip performance, particularly for AI chips [3][7] - TSMC's CoWoS technology is currently monopolizing the advanced AI chip packaging market, with a projected compound annual growth rate of 40% for the advanced packaging market in the coming years [7][10] Group 2 - TSMC plans to increase its CoWoS production capacity from 36,000 wafers per month in 2024 to 90,000 by the end of this year and aims for 130,000 by 2026 [8] - The core challenge in CoWoS technology lies in achieving high yield rates during the packaging process, which is crucial for minimizing losses in HBM and other devices [10][14] - Domestic companies are actively developing similar CoWoS packaging technologies, with key players including Shenghe Jingwei and Tongfu Microelectronics, both facing common industry challenges [18][19] Group 3 - Shenghe Jingwei is recognized as a leading player in advanced packaging in China, focusing on Chiplet packaging and achieving significant revenue growth, with a reported revenue of $270 million in 2022 [19] - Tongfu Microelectronics primarily serves the domestic market and has faced challenges in overseas collaborations, including a failed partnership with AMD for CoWoS packaging [20][21] - Other companies, such as Yongxi Electronics, are also entering the advanced packaging market, leveraging their existing 2.5D packaging technology to potentially expand into HBM packaging [22][23]

Core Viewpoint - The discussion highlights the transformative impact of artificial intelligence (AI) on society, scientific discovery, and the importance of foundational knowledge for the younger generation in adapting to the AI era [1][5][7]. Group 1: AI Development Trends - The next trend in AI development is its penetration into the physical world, transitioning from "perceptual AI" to "generative AI" and now to "reasoning AI," which can understand and generate information [2][3]. - The upcoming wave is "physical AI," which will be applied in robotics and other physical machines, enhancing human capabilities [3]. Group 2: China's Role in AI - China plays a significant role in AI development, with the highest number of research papers published globally. The country excels in open-source projects, which have a global impact [4]. - Open-source models like DeepSeek and Tongyi Qianwen are among the top in the world, benefiting various sectors such as healthcare and finance [4]. Group 3: AI's Impact on Scientific Discovery - AI is poised to revolutionize scientific discovery by enabling a deeper understanding of biological processes, which could lead to advancements in drug design and longevity [5]. - The ability to understand the structure and significance of biological entities through AI presents substantial opportunities [5]. Group 4: Future of Chip Technology - The future of chip technology involves the development of three-dimensional transistors and advanced packaging techniques, with significant innovations expected in silicon photonics [5]. - The transition from single chips to stacked and multi-chip designs is a key focus area for the next two decades [5]. Group 5: Advice for the Younger Generation - Young individuals are encouraged to master foundational skills such as mathematics, reasoning, logic, and programming to effectively interact with AI [6][7]. - Critical thinking is essential for evaluating AI-generated answers, and understanding first principles is crucial for problem-solving [7].

Core Viewpoint - The discussion highlights the transformative impact of artificial intelligence (AI) on society, scientific discovery, and the future of chip technology, emphasizing the importance of foundational knowledge for the younger generation in adapting to the AI era [3][5][9]. Group 1: AI Development and Trends - AI is evolving from "perceptual AI" to "generative AI," with capabilities now extending to understanding and generating information across different modalities [5]. - The next wave of AI development is expected to penetrate the physical world, leading to advancements in robotics and other physical machines [5]. - Huang emphasized the significance of "reasoning AI," which can understand and solve complex problems previously unencountered [5]. Group 2: China's Role in AI - Huang noted that China leads the world in the number of research papers published in AI, showcasing its significant contributions to open-source projects [6]. - Open-source models developed in China, such as DeepSeek and Tongyi Qianwen, are recognized as top-tier globally, benefiting various sectors including healthcare and finance [6]. Group 3: AI's Impact on Scientific Discovery - AI is poised to revolutionize scientific discovery by aiding in the understanding of biological structures and processes, which could lead to breakthroughs in drug design and longevity [7]. - Huang highlighted the potential of AI to interpret complex biological data, which could unlock significant opportunities in medicine [7]. Group 4: Future of Chip Technology - Huang discussed the future of chip technology, predicting a shift towards three-dimensional transistors and advanced packaging techniques, such as "CoWoS" [7]. - Innovations in silicon photonics are also anticipated, indicating a promising future for chip development [7]. Group 5: Advice for the Younger Generation - Huang advised young people to focus on mastering foundational skills such as mathematics, reasoning, logic, and programming to effectively engage with AI [9]. - He stressed the importance of critical thinking to evaluate AI-generated answers and to articulate problems clearly when interacting with AI [9].

Core Viewpoint - UBS maintains a "Buy" rating for TSMC and raises the target price from NT$1,180 to NT$1,200, highlighting the company's growth potential driven by capacity expansion, financial forecasts, and industry trends [1][5] Group 1: Capacity Expansion and Strategic Positioning - TSMC's annual capacity is projected to reach 36 million 8-inch equivalent wafers by the end of 2023, with a production network spanning Taiwan and overseas [1] - The company operates four 12-inch and four 8-inch fabs in Taiwan, along with a 12-inch fab and two 8-inch fabs in the U.S. and China, ensuring supply chain stability and geopolitical risk mitigation [1] Group 2: Financial Performance and Projections - UBS raises TSMC's 2025 revenue growth forecast from 25% to 29%, with capital expenditure expectations adjusted to a range of $40 billion to $42 billion, driven by surging cloud AI demand and advanced process capacity [2] - The gross margin is expected to remain high at 57.0%, close to the historical peak of 58.8% in the previous quarter, with long-term EPS growth rate estimates increased from 16% to 18% [2] Group 3: AI Demand and Packaging Technology - Despite a downward revision in smartphone and PC shipment forecasts, optimism remains for cloud AI chip demand, with TSMC's CoWoS packaging capacity expected to reach 70,000 pieces per month by the end of 2025 and 100,000 pieces by the end of 2026, a 30% increase from previous plans [3] - This expansion is anticipated to alleviate supply concerns for high-end AI chips and boost the revenue share from packaging services [3] Group 4: Profitability and Cost Management - TSMC is expected to maintain a gross margin of 55.5% to 56.5% from Q3 2025 to 2026, significantly above market consensus of 53% to 55%, due to strategic price adjustments and supply chain management [3] - Price increases for N5 and N3 wafers are planned, with mobile products seeing a 3%-5% increase and HPC products up by 10% [3] Group 5: Capital Expenditure Strategy - TSMC plans to increase capital expenditure for N2 process and overseas expansion, with external capital expenditure expected to reach $40 billion in 2025, a 5% increase from previous plans [4] - This strategy aims to reinforce TSMC's technological leadership and prepare for the restructuring of the global semiconductor supply chain [4] Group 6: Valuation and Investment Recommendation - UBS maintains a "Buy" rating for TSMC, raising the 12-month target price to NT$1,200 based on stronger AI demand and cost management capabilities [5] - The current stock price of NT$1,055 corresponds to a 2025 P/E ratio of only 22 times, significantly lower than its long-term growth expectations, making TSMC a compelling choice for investors seeking core assets in the semiconductor industry [5]

Core Viewpoint - The article discusses the evolution and significance of TSMC's CoWoS packaging technology, particularly in relation to NVIDIA's increasing reliance on CoWoS-L for its Blackwell architecture, highlighting the challenges and advancements in the semiconductor industry [1][2][5]. Group 1: TSMC and NVIDIA Collaboration - TSMC has become a crucial partner for NVIDIA, especially in the CoWoS packaging technology, with NVIDIA's CEO stating that they have no alternative to TSMC for this advanced technology [1]. - TSMC has reportedly surpassed ASE Group to become the largest player in the global packaging and testing market, driven by the demand for advanced packaging solutions [1]. Group 2: CoWoS Technology Evolution - NVIDIA plans to increase the use of CoWoS-L packaging for its upcoming Blackwell series products, transitioning from CoWoS-S to meet the high bandwidth requirements of its GPUs [2]. - The CoWoS technology faces challenges due to the increasing chip sizes, which limit the number of chips that can be placed on a 12-inch wafer, and the associated thermal management issues [5]. Group 3: Innovations and Challenges - TSMC is exploring the use of flux-free bonding technology to address issues related to flux residue that can affect chip reliability, with testing expected to be completed by the end of the year [6]. - The current interposer size in TSMC's CoWoS packaging is 80x80mm, with plans to introduce larger sizes by 2026 and 2027, which may enhance performance but also pose design challenges [8]. Group 4: Future Technologies - TSMC is betting on CoPoS technology, which replaces the traditional wafer with a panel, allowing for greater chip density and efficiency, with plans for mass production by 2029 [9][10]. - CoPoS is positioned as a potential alternative to CoWoS-L, offering advantages in signal integrity and power transmission, particularly for high-performance applications [11]. Group 5: Market Implications - The shift from circular wafers to square panels in CoPoS technology is expected to significantly enhance production capacity and cost efficiency, making it competitive in AI, 5G, and high-performance computing sectors [12]. - Despite the advantages, the transition to CoPoS requires substantial investment in materials and equipment, and overcoming technical challenges related to precision and yield will be critical for its success [13].

Core Viewpoint - The article discusses the significant rise of TSMC's CoWoS packaging technology, driven by the increasing demand for GPUs in the AI sector, particularly through its partnership with NVIDIA, which has deepened over time [1][3]. Group 1: CoWoS Technology and NVIDIA Partnership - NVIDIA has emphasized its reliance on TSMC for CoWoS technology, stating that it has no alternative partners in this area [1]. - TSMC has reportedly surpassed ASE Group to become the largest player in the global packaging market, benefiting from the growing demand for advanced packaging solutions [1]. - NVIDIA's upcoming Blackwell series will utilize more CoWoS-L packaging, indicating a shift in production focus from CoWoS-S to CoWoS-L to meet the high bandwidth requirements of its GPUs [3]. Group 2: Challenges and Innovations in CoWoS - The increasing size of AI chips poses challenges for CoWoS packaging, as larger chips reduce the number of chips that can fit on a 12-inch wafer [4]. - TSMC is facing difficulties with the use of flux in CoWoS, which is essential for chip bonding but becomes problematic as the size of the interposer increases [4][5]. - TSMC is exploring flux-free bonding technologies to improve yield rates and address the challenges posed by flux residue [5]. Group 3: Future Developments and Alternatives - TSMC plans to introduce CoWoS-L with a mask size of 5.5 times larger by 2026 and aims for a record 9.5 times larger version by 2027 [8]. - The company is also developing CoPoS technology, which replaces traditional wafers with panel substrates, allowing for higher chip density and efficiency [9][10]. - CoPoS is positioned as a potential alternative to CoWoS-L, targeting high-performance applications in AI and HPC systems [12]. Group 4: Technical Comparisons - FOPLP and CoPoS both utilize large panel substrates but differ in architecture; FOPLP does not use an interposer, while CoPoS does, enhancing signal integrity for high-performance chips [11]. - CoPoS is transitioning to glass substrates, which offer better performance characteristics compared to traditional organic substrates [12]. - The shift from round wafers to square panels in CoPoS aims to improve yield and reduce costs, making it more competitive in the AI and 5G markets [12]. Group 5: Challenges Ahead - Transitioning to square panel technology requires significant investment in materials and equipment, along with overcoming technical challenges related to pattern precision [14]. - The demand for finer RDL line widths poses additional challenges for suppliers, necessitating breakthroughs in RDL layout technology [14]. Conclusion - The future of TSMC's packaging technologies appears promising, with ongoing innovations and adaptations to meet the evolving demands of the semiconductor industry [14].

Core Viewpoint - The article discusses the significant advancements and challenges in TSMC's CoWoS (Chip-on-Wafer-on-Substrate) packaging technology, particularly in relation to NVIDIA's evolving needs in the AI sector, highlighting the shift towards CoWoS-L and the emergence of CoPoS (Chip-on-Panel-on-Substrate) as a potential alternative [1][3][11]. Group 1: TSMC and NVIDIA Collaboration - TSMC has become a crucial partner for NVIDIA, especially in the CoWoS technology, with NVIDIA's CEO stating that they have no alternative to TSMC in this area [1]. - NVIDIA is transitioning to use more CoWoS-L packaging for its upcoming Blackwell series products, which require high bandwidth interconnects [3][6]. Group 2: CoWoS Technology Developments - TSMC has been expanding its CoWoS capacity significantly over the past two years and is reportedly surpassing ASE Group to become the largest packaging player globally [1]. - The CoWoS technology is evolving, with TSMC planning to introduce CoWoS-L with a mask size of 5.5 times by 2026 and a record 9.5 times by 2027 [9]. Group 3: Challenges in CoWoS Technology - The increasing chip sizes pose challenges for CoWoS packaging, as larger chips reduce the number of chips that can fit on a 12-inch wafer [6]. - TSMC is facing difficulties with flux usage in CoWoS, which is essential for chip bonding, and is exploring flux-free bonding technologies [7][9]. Group 4: Emergence of CoPoS Technology - CoPoS technology is being developed as a next-generation alternative to CoWoS, allowing for higher chip density and efficiency by using a panel instead of a wafer [11][14]. - TSMC's AP7 factory is set to become a key hub for advanced packaging, focusing on CoPoS production [12]. Group 5: Comparison of FOPLP and CoPoS - FOPLP (Fan-out Panel-Level Packaging) and CoPoS both utilize large panel substrates but differ in architecture and application, with CoPoS offering better signal integrity due to its use of an interposer [12][13]. - CoPoS is positioned for high-end applications in AI and HPC systems, while FOPLP is more suited for mid-range applications [13][14].

Core Viewpoint - The article discusses the significant advancements and challenges in TSMC's CoWoS (Chip-on-Wafer-on-Substrate) packaging technology, particularly in relation to NVIDIA's evolving needs in the AI sector, highlighting the shift towards CoWoS-L and the emergence of CoPoS (Chip-on-Panel-on-Substrate) as a potential alternative [1][3][10]. Group 1: TSMC and NVIDIA Collaboration - TSMC has become a crucial partner for NVIDIA, especially in the CoWoS domain, with NVIDIA's CEO Jensen Huang stating that they have no alternative to TSMC for this advanced packaging technology [1]. - NVIDIA is transitioning to use more CoWoS-L packaging for its latest Blackwell series products, which require high bandwidth interconnects between chips [3][5]. Group 2: CoWoS Technology Evolution - The CoWoS technology is facing challenges due to increasing chip sizes, with AI chips potentially reaching dimensions of 80x84 mm, limiting the number of chips per wafer [5]. - TSMC is exploring alternatives to traditional solder paste bonding methods due to difficulties in maintaining yield rates, including the development of no-solder paste bonding technology [6][9]. Group 3: Future Developments in Packaging - TSMC plans to introduce CoWoS-L with a mask size of 5.5 times the current size by 2026, and a record 9.5 times mask size CoWoS by 2027 [9]. - CoPoS technology is being developed as a next-generation packaging solution, with plans for mass production by 2029, aiming to enhance efficiency and reduce costs by utilizing larger rectangular substrates [12][14]. Group 4: Comparison of Packaging Technologies - CoPoS differs from FOPLP (Fan-out Panel-Level Packaging) in that it uses an interposer for better signal integrity and power delivery, making it suitable for high-performance applications [13]. - The transition from traditional organic substrates to glass substrates in CoPoS is expected to improve interconnect density and thermal stability, positioning it as a potential successor to CoWoS-L [14].

Core Viewpoint - TSMC is expected to become the world's largest packaging supplier, surpassing ASE, with advanced packaging revenue projected to account for 10% of total revenue this year due to the surge in demand for AI chips using CoWoS technology [1] Group 1: CoWoS Technology Development - TSMC's recent technology seminar highlighted the next steps in CoWoS technology, indicating a potential technological revolution and intense cross-industry competition [1] - The new CoWoS structure will integrate more functionalities, including an integrated voltage regulator (IVR), which is a significant advancement over previous designs [3][4] - The IVR will be embedded within the silicon interposer, presenting technical challenges in terms of size and performance requirements [5] Group 2: Industry Implications - TSMC's dominance in advanced packaging could threaten the existence of independent power module suppliers like Delta and Infineon, as their products may be integrated into TSMC's CoWoS solutions [4][8] - The shift towards integrating more functions into chips could lead to a reshuffling of market positions among suppliers in the data center market, with Nvidia and TSMC taking the lead [8][9] Group 3: Power Supply Architecture - The power requirements for future AI servers are substantial, with single racks potentially consuming up to 1MW, necessitating a complete overhaul of power supply architectures [8] - TSMC and Nvidia are promoting an 800V high-voltage direct current (HVDC) power system to improve efficiency and reduce heat generation in AI data centers [8] - The transition to this new power architecture may lead to significant changes in supplier relationships, as companies like Infineon prioritize their own needs over external sales [9]