Core Viewpoint - Leading foundries and IDM manufacturers are advancing towards the production of 2nm (or equivalent) technology nodes, with GAA (Gate-All-Around) nanosheet transistors playing a crucial role in this transition [1][2]. Group 1: GAA Nanosheet Technology - GAA nanosheet devices are designed to further reduce the size of SRAM and logic standard cells by vertically stacking two or more nanosheet-like conductive channels [1]. - The configuration allows designers to minimize the height of logic standard cells while enhancing gate control over the channel, even at shorter channel lengths [1]. - GAA nanosheet technology is expected to last at least three generations before transitioning to CFET (Complementary FET) technology, with the A10 node anticipated to have a cell height as low as 90nm [2]. Group 2: Forksheet Device Architecture - Forksheet device architecture, introduced by imec, offers greater scalability compared to conventional GAA nanosheet technology [4][5]. - The inner wall forksheet structure allows for tighter n-to-p spacing, enabling further reduction in cell area while still providing performance improvements [5]. - imec demonstrated the manufacturability of the 300mm inner wall forksheet process flow, confirming its potential to extend the roadmap for logic and SRAM nanosheets to the A10 node [6]. Group 3: Challenges and Improvements - Despite successful hardware demonstrations, concerns regarding the manufacturability of the inner wall forksheet architecture led imec to reconsider its design [6][8]. - The outer wall forksheet design, presented at VLSI 2025, aims to reduce process complexity while maintaining performance and area scalability [9][11]. - The outer wall forksheet allows for a thicker dielectric wall (up to 15nm) without affecting the 90nm cell height, simplifying the integration process [11][16]. Group 4: Performance and Power Advantages - The outer wall forksheet is expected to provide significant advantages over the inner wall design in five key areas, including improved gate control and reduced parasitic capacitance [14][18]. - A benchmark study indicated that the area of SRAM cells based on the outer wall forksheet is reduced by 22% compared to A14 nanosheet architecture [25]. - The ability to achieve full channel strain in the outer wall forksheet design is anticipated to enhance performance, particularly in driving current [19][25]. Group 5: Future Outlook - imec is currently exploring the compatibility of the outer wall forksheet design with CFET architecture and the potential PPA benefits that could arise from this innovative scaling booster [27].

Core Viewpoint - Leading foundries and IDM manufacturers are advancing towards the production of 2nm (or equivalent) technology nodes, with GAA (Gate-All-Around) nanosheet transistors playing a crucial role in this transition [1][2]. Group 1: GAA Nanosheet Technology - GAA nanosheet devices feature vertically stacked conductive channels, allowing for further reduction in the height of logic standard cells, defined as the number of metal lines multiplied by the metal pitch [1]. - GAA nanosheet transistors provide enhanced gate control over the channel, even at shorter channel lengths, compared to FinFET technology [1]. - The transition to CFET (Complementary FET) technology is expected to occur after at least three generations of GAA nanosheet technology, with GAA expected to extend to the A10 technology node, where cell heights could reach as low as 90nm [2]. Group 2: Forksheet Device Architecture - The forksheet device architecture was introduced by imec in 2017 as a scaling booster for SRAM units and later for logic standard cells, featuring a dielectric wall between nMOS and pMOS devices [4]. - The "inner wall" forksheet configuration allows for tighter n-to-p spacing, enabling further area reduction while still providing performance improvements [4]. - imec demonstrated the manufacturability of the 300mm inner wall forksheet process flow, confirming its potential to extend the roadmap for logic and SRAM nanosheets to the A10 node [6]. Group 3: Challenges and Improvements - Despite successful hardware demonstrations, concerns regarding manufacturability have led imec to reconsider the original forksheet architecture, particularly the dielectric wall's thickness and its impact on subsequent fabrication steps [8]. - The introduction of the "outer wall" forksheet design aims to reduce process complexity while maintaining performance and area scalability [10]. - The outer wall forksheet allows for a wider dielectric wall (up to approximately 15nm) without affecting the 90nm cell height, simplifying the integration process [12]. Group 4: Performance and Power Advantages - The outer wall forksheet design is expected to provide better gate control compared to the inner wall design, enhancing the overall performance of the devices [14]. - A benchmark study indicated that the area of SRAM units based on the outer wall forksheet is reduced by 22% compared to A14 nanosheet architecture, highlighting its area advantage [25]. - The ability to achieve effective source/drain stress in outer wall forksheet devices is anticipated to yield further performance benefits in ring oscillator designs [25].

Core Viewpoint - The article discusses the advancements in semiconductor technology, particularly focusing on the transition to 2nm technology nodes and the role of Gate-All-Around (GAA) nanosheet transistors in this evolution [1][2][30]. Group 1: GAA Nanosheet Technology - GAA nanosheet devices are positioned as successors to FinFET technology, allowing for further miniaturization of SRAM and logic standard cells [1]. - The GAA architecture features vertically stacked nanosheet channels, enhancing gate control over the channel even at shorter channel lengths [1][2]. - The transition to Complementary FET (CFET) technology is expected to occur after at least three generations of GAA nanosheet technology [2]. Group 2: Forksheet Device Architecture - Forksheet architecture was introduced by imec as a scaling booster for SRAM and logic standard cells, allowing for tighter n-to-p spacing and further area reduction [4][5]. - The inner wall forksheet design initially faced manufacturability challenges, particularly regarding the thin dielectric wall required for achieving a 90nm logic standard cell height [7]. - The outer wall forksheet design was developed to address these challenges, simplifying the manufacturing process while maintaining performance and area scaling advantages [9][11][30]. Group 3: Performance and Integration - The outer wall forksheet design allows for improved gate control and reduced parasitic capacitance compared to traditional nanosheet devices [15][16]. - The wall-last integration method enables effective source/drain stress sources, enhancing performance through full channel strain [21][22]. - A benchmark study indicated that the outer wall forksheet SRAM unit area is reduced by 22% compared to A14 nanosheet architecture, demonstrating significant area efficiency [26]. Group 4: Future Outlook - imec is exploring the compatibility of the outer wall forksheet design with CFET architecture, aiming to leverage the PPA benefits from this innovative scaling booster [30].