Core Viewpoint - Intel's new CEO, Lip-Bu Tan, is considering significant changes to the company's contract manufacturing business to attract major clients, which may incur high costs compared to previous plans [1][2]. Group 1: Strategic Changes - The new strategy for Intel's contract manufacturing will not include marketing certain long-developed chip manufacturing technologies to external clients [1]. - Intel's 18A process, which has seen substantial investment, is reportedly losing appeal to new customers, prompting the need for potential write-downs [1][2]. - The company is focusing more resources on the 14A process, which is expected to be more competitive than TSMC's N2 technology, aiming to attract major clients like Apple and Nvidia [2]. Group 2: Financial Implications - Intel is projected to incur losses of up to $18.8 billion in 2024, marking its first loss since 1986 [3]. - The potential costs associated with the shift in strategy could lead to losses in the hundreds of millions or even billions of dollars [1][2]. Group 3: Production Plans - Intel plans to achieve mass production of the 18A chips later this year, with internal chips expected to be delivered ahead of external customer orders [4]. - The timely delivery of 14A chips to secure large contracts remains uncertain, and Intel may continue with its existing 18A chip plans [4][5].

Core Viewpoint - Leading foundries and IDM manufacturers are advancing towards the production of 2nm (or equivalent) technology nodes, with GAA (Gate-All-Around) nanosheet transistors playing a crucial role in this transition [1][2]. Group 1: GAA Nanosheet Technology - GAA nanosheet devices are designed to further reduce the size of SRAM and logic standard cells by vertically stacking two or more nanosheet-like conductive channels [1]. - The configuration allows designers to minimize the height of logic standard cells while enhancing gate control over the channel, even at shorter channel lengths [1]. - GAA nanosheet technology is expected to last at least three generations before transitioning to CFET (Complementary FET) technology, with the A10 node anticipated to have a cell height as low as 90nm [2]. Group 2: Forksheet Device Architecture - Forksheet device architecture, introduced by imec, offers greater scalability compared to conventional GAA nanosheet technology [4][5]. - The inner wall forksheet structure allows for tighter n-to-p spacing, enabling further reduction in cell area while still providing performance improvements [5]. - imec demonstrated the manufacturability of the 300mm inner wall forksheet process flow, confirming its potential to extend the roadmap for logic and SRAM nanosheets to the A10 node [6]. Group 3: Challenges and Improvements - Despite successful hardware demonstrations, concerns regarding the manufacturability of the inner wall forksheet architecture led imec to reconsider its design [6][8]. - The outer wall forksheet design, presented at VLSI 2025, aims to reduce process complexity while maintaining performance and area scalability [9][11]. - The outer wall forksheet allows for a thicker dielectric wall (up to 15nm) without affecting the 90nm cell height, simplifying the integration process [11][16]. Group 4: Performance and Power Advantages - The outer wall forksheet is expected to provide significant advantages over the inner wall design in five key areas, including improved gate control and reduced parasitic capacitance [14][18]. - A benchmark study indicated that the area of SRAM cells based on the outer wall forksheet is reduced by 22% compared to A14 nanosheet architecture [25]. - The ability to achieve full channel strain in the outer wall forksheet design is anticipated to enhance performance, particularly in driving current [19][25]. Group 5: Future Outlook - imec is currently exploring the compatibility of the outer wall forksheet design with CFET architecture and the potential PPA benefits that could arise from this innovative scaling booster [27].

Group 1 - The core viewpoint is that ASML dominates the photolithography market, holding over 80% market share, particularly in the high-end EUV lithography machines, which are essential for manufacturing chips below 7nm [1] - Global companies are seeking alternatives to bypass ASML's monopoly, especially regarding EUV technology, which could potentially reshape the semiconductor equipment landscape [3] - Various alternative technologies have been proposed, including Japan's NIL nanoimprint technology and the US's EBL electron beam technology, which are claimed to be capable of producing 5nm chips [5] Group 2 - The University of Southampton in the UK has announced the establishment of the first advanced electron beam lithography center with a resolution below 5nm, marking a significant development in chip manufacturing technology that does not rely on EUV machines [5][7] - The current electron beam lithography technology is limited to 200mm wafers (8 inches), with future advancements needed to support 300mm (12 inches) wafers [7] - If breakthroughs in electron beam lithography are achieved, ASML may face significant challenges, leading to a potential reshuffling of the current market dynamics [7]