Core Viewpoint - The long-term proposition of DRAM is transitioning from 2D to 3D architecture, with NPU as a co-processor likely to be the next trend in edge technology when combined with 3D DRAM [1][2][4]. Industry Insights and Investment Recommendations - The integration of NPU as a co-processor with 3D DRAM is expected to be a significant trend in edge technology, leading to an "overweight" rating for the industry [2]. - Current advancements in DRAM technology face challenges as the process node has reached 10nm, making it increasingly difficult to achieve stable charge storage and read/write operations in smaller spaces [3]. - The hybrid bonding method improves stacking height limitations and is seen as the future technical path for 3D DRAM, allowing for more stacked layers and better thermal management compared to existing Micro bump technology [3]. AI Application and Memory Bandwidth - AI applications are diversifying rather than conforming to a unified model, with hardware developments paving the way for new technologies that support AI's ubiquitous and always-on capabilities [4]. - The primary bottleneck for AI edge inference speed is memory bandwidth rather than computational power, with 3D DRAM addressing memory limitations effectively [5]. - For instance, Qualcomm's Snapdragon 8 GEN 3 has a computational capability of approximately 45 TOPs and a memory bandwidth of about 67 GB/s, highlighting the significant impact of memory bandwidth on performance [5].

Group 1 - The core viewpoint of the report is that the transition from 2D to 3D architecture in DRAM is essential due to the challenges faced in further miniaturization of DRAM processes, with hybrid bonding technology representing the future path for 3D DRAM [1] - The report highlights that the current bottleneck in AI edge inference speed is memory bandwidth rather than computing power, and that 3D DRAM can significantly enhance transmission efficiency [1][3] - The use of NPU as a co-processor combined with 3D DRAM is likely to be the next trend in edge technology, with companies like Zhaoyi Innovation (兆易创新) being recommended for investment [1][2] Group 2 - AI applications are diversifying rather than conforming to a unified model, with new hardware technologies being developed to support this trend, particularly through the use of smaller models that outperform larger ones [2] - The report indicates that the memory bandwidth limitation is significantly greater than the computational limitation, as demonstrated by the Snapdragon 8 GEN3 example, where memory bandwidth constraints are evident [3] - Major players in the industry, including Zhaoyi Innovation and its subsidiaries, as well as Taiwanese storage IDM Winbond and Qualcomm, are focusing on the 3D DRAM and NPU solution, indicating a clear technological trend [3]

Core Viewpoint - The current bottleneck in inference speed is primarily due to memory bandwidth rather than computing power, with the NPU+DRAM stacking technology showing significant improvements in memory bandwidth, indicating a clear industry trend [1][2]. Group 1: Inference Speed and Memory Bandwidth - The Qualcomm Snapdragon 8 GEN 3 has an NPU computing power of approximately 45 TOPs and a memory bandwidth of about 67 GB/s. When running a 7B large model, the calculation capability is limited to approximately 3215 tokens/s by computing power and 4.8 tokens/s by memory bandwidth, with the final speed being constrained by the lower of the two values, highlighting the significant memory bandwidth limitation [2]. - A practical test on a Xiaomi phone using the Qwen3-8B-MNN model showed a decoding speed of 222 tokens with an average response time of 32 seconds, indicating that a user-perceived inference speed should reach 40-50 tokens/s [2]. Group 2: 3D DRAM Solution - The memory limitation for edge AI can be addressed by 3D DRAM. By stacking DRAM and NPU through HB technology, if the memory bandwidth is increased to 800 GB/s, the memory limitation could rise to 57 tokens/s [3]. - Key players in this space include Chinese companies like Zhaoyi Innovation and its subsidiary Qingyun Technology, as well as Taiwanese storage IDM Winbond and mobile AP leader Qualcomm, all focusing on the 3D DRAM+NPU solution, indicating a clear technological trend [3]. Group 3: Hardware and Model Development - The current industry phase suggests that hardware is leading model development, with future growth expected to be driven by model advancements benefiting from hardware improvements. Hardware solutions require extensive stability testing before commercial deployment at scale [3]. - Qualcomm must adopt strategies suitable for AI large model devices to avoid risks associated with a potential "GPU" revolution in mobile AI by the end of 2025 or 2026, as companies prepared with the right hardware and models could experience a significant one-year window of opportunity [3].