Core Viewpoint - TSMC has quietly announced the commencement of volume production of its N2 (2nm) process chips, achieving its previously stated goal for production in Q4 2025 [1][5]. Group 1: N2 Technology Overview - TSMC's N2 technology utilizes the first-generation nanosheet transistor technology, enhancing performance and power efficiency across all nodes [1]. - The N2 process aims for a 10%-15% performance improvement at the same power consumption and a 25%-30% reduction in power consumption at the same performance level [3][4]. - For mixed designs including logic, analog, and SRAM, transistor density is expected to increase by 15% compared to N3E, while pure logic designs will see a 20% increase [3]. Group 2: Production and Capacity - TSMC has begun production at its Fab 22 facility near Kaohsiung, Taiwan, with expectations for ramping capacity in 2026 driven by demand from smartphones and high-performance computing AI applications [5]. - The company is also constructing two new fabs capable of N2 process technology to meet the strong interest from partners, with plans to produce N2P and A16 chips starting in the second half of 2026 [7]. Group 3: Performance Enhancements - The N2P process, an enhanced version of N2, is set to further improve performance and power efficiency, while the A16 variant will utilize a Super Power Rail design tailored for complex AI and HPC processors [7].

Core Viewpoint - TSMC has quietly announced the commencement of volume production of its N2 (2nm) process technology, achieving its goal set for Q4 2025 without a formal press release [1][5]. Group 1: N2 Technology Overview - The N2 process utilizes the first-generation nanosheet transistor technology, providing significant improvements in performance and power consumption [1]. - TSMC's N2 technology is expected to be the most advanced in the semiconductor industry in terms of density and energy efficiency, addressing the growing demand for energy-efficient computing [1]. - The N2 design aims for a 10%-15% performance increase at the same power level and a 25%-30% reduction in power consumption at the same performance level [3][4]. Group 2: Performance Metrics - For mixed designs including logic, analog, and SRAM, transistor density is expected to increase by 15% compared to N3E, while pure logic designs will see a 20% increase [3][4]. - The N2 process will feature a significant reduction in power consumption, with estimates ranging from 25% to 30% compared to N3E [4]. Group 3: Production and Capacity - TSMC has begun production of 2nm chips at its Fab 22 facility near Kaohsiung, Taiwan, with expectations for ramp-up in capacity driven by demand from smartphones and high-performance computing AI applications in 2026 [5][8]. - The company is constructing two new fabs capable of N2 technology to meet the strong interest from partners, with plans to produce N2P and A16 chips starting in late 2026 [8]. Group 4: Future Developments - TSMC plans to introduce N2P, an enhanced version of the N2 process, which will further improve performance and power efficiency, with volume production expected in the second half of 2026 [8]. - The A16 chip, designed for complex AI and HPC processors, will also begin production in the second half of 2026, utilizing TSMC's advanced Super Power Rail design [8].