Core Viewpoint - Changfei Fiber's stock surged by the daily limit of 10% within three minutes of market opening, marking its fourth consecutive day of gains, closing at 82.95 yuan per share. This increase is attributed to rumors regarding the synergy between Changfei's hollow fiber products and Nvidia's Ethernet technology, which has reportedly been procured by Nvidia [1]. Company Summary - Changfei Fiber's hollow fiber products are aligned with the needs of data center construction, which is a core area for Nvidia's products. However, there is no direct supplier-customer relationship between Changfei and Nvidia [1].

Core Viewpoint - The article discusses the development trends of intelligent computing chips and edge AI chips amidst the AI boom, highlighting the challenges and solutions in testing high-speed chips and the importance of interface compatibility in consumer-side chips [1]. Group 1: Event Overview - The seminar on high-speed chip testing technology will be held on May 21, organized by Nanjing Integrated Circuit Industry Service Center (ICisC) and Keysight [1]. - The event aims to explore popular semiconductor technologies for 2025 and testing methods for high-speed chips, covering PCIe 5.0/6.0, Ethernet, MIPI, and USB technologies [1]. Group 2: Seminar Highlights - The seminar will feature expert discussions on high-speed interface testing technologies, with opportunities for attendees to ask questions [2]. - Attendees will have the chance to observe high-speed chip testing processes in the ICisC laboratory [2]. - The event encourages deep exchanges among professionals in chip design, IP, EDA, and packaging sectors [2]. Group 3: Agenda - The agenda includes a welcome speech, an introduction to ICisC platform business, discussions on key technologies and measurement of intelligent computing chips, post-silicon validation of SoC chip interfaces, challenges in consumer-side chip testing, and a technical salon [9].

Core Insights - The article discusses the development trends of intelligent computing chips and edge AI chips amidst the AI boom, highlighting the increasing demand for high-speed chips and the challenges in testing them [1] Group 1: Event Overview - The event titled "Keysight & Nanjing ICisC High-Speed Chip Testing Technology Seminar" will take place on May 21, focusing on semiconductor technologies popular in 2025 and testing methods for high-speed chips [1] - The seminar will cover topics such as PCIe 5.0/6.0 technology, Ethernet technology, MIPI, and USB technology, with live demonstrations of high-speed chip testing [1][2] Group 2: Agenda Highlights - The agenda includes a welcome speech, an introduction to the Nanjing Integrated Circuit Industry Service Center (ICisC), discussions on key technologies and measurement for intelligent computing chips, and challenges in testing consumer-side chips [9] - There will be a tea break and opportunities for free communication among participants, followed by a technical salon [9] Group 3: Participant Benefits - Attendees will receive practical gifts such as Xiaomi backpacks, with limited availability on a first-come, first-served basis [2][5][7]

Core Insights - The article discusses the development trends of intelligent computing chips and edge AI chips amidst the AI boom, highlighting the increasing demand for high-speed chips and the challenges in testing them [1] - A seminar on high-speed chip testing technology will be held on May 21, organized by Nanjing Integrated Circuit Industry Service Center (ICisC) and Keysight Technologies, focusing on semiconductor technologies popular in 2025 [1][9] Event Details - The seminar will take place on May 21 from 13:30 to 17:30 at Nanjing Jiangbei New District, featuring expert discussions on PCIe 5.0/6.0, Ethernet, MIPI, and USB testing technologies [2][9] - Attendees will have the opportunity to observe high-speed chip testing processes in the ICisC laboratory [2][9] Agenda Highlights - The agenda includes a welcome address, an introduction to ICisC platform business, discussions on key technologies and measurements for intelligent computing chips, post-silicon validation of SoC chip high-speed interfaces, and challenges in testing consumer-side chips [8][9] - The event will also feature a technical salon for in-depth discussions and networking opportunities among professionals in chip design, IP, EDA, and packaging [2][8]