Core Viewpoint - TSMC plans to build four advanced packaging (AP) factories to address capacity shortages and maintain its competitive edge in the semiconductor industry, particularly in advanced packaging technologies like CoWoS [1][4][11] Group 1: TSMC's Expansion Plans - TSMC will announce the expansion of four advanced packaging factories in Tainan, including locations in Chiayi Science Park and Southern Science Park [1] - The company aims to start mass production at its AP factory 1 in the Ziyi Technology Park in the first half of this year [1] - TSMC's expansion is a response to concerns about its potential transformation into "American TSMC" due to recent factory expansions in the U.S. [1] Group 2: Industry Trends and Challenges - The global tech industry is facing intense competition for advanced packaging technology, particularly TSMC's CoWoS, which is critical for connecting high-performance chips with ultra-fast memory [4][9] - By 2026, the bottleneck in AI GPU supply will shift from chip shortages to the complex assembly processes required for advanced packaging [4][9] - The transition from wafer-level packaging (WLP) to fan-out panel-level packaging (FOPLP) is expected to increase processing capacity significantly [11] Group 3: Strategic Implications - NVIDIA has secured nearly 60% of TSMC's CoWoS capacity for 2026, influencing competitors like AMD and Broadcom to vie for the remaining capacity [7] - The advanced packaging secondary market is rapidly maturing, with companies like Intel positioning their packaging technologies as alternatives to TSMC [8] - The industry's reliance on TSMC for advanced packaging creates vulnerabilities, as geopolitical stability in the Taiwan Strait remains a critical factor for the global AI economy [8][12] Group 4: Future Outlook - The industry's focus is shifting towards the physical realities of AI hardware, with advanced packaging becoming a crucial factor in the growth of AI capabilities [9][10] - Upcoming challenges include the transition to glass substrates for improved interconnect density and thermal management, which could disrupt TSMC's current dominance [11] - The success of HBM4 chip yields and the ramp-up of TSMC's AP7 capacity will be closely monitored, as delays could impact the release of next-generation AI models [12]

Core Viewpoint - Hybrid bonding technology is rapidly transitioning from laboratory to mass production, becoming a new pillar in storage chip manufacturing, particularly in the context of advanced packaging technologies like 3D NAND and HBM [2][3]. Group 1: Hybrid Bonding Technology - Hybrid bonding eliminates size limitations and parasitic effects associated with traditional bump structures, resulting in shorter signal transmission paths, lower power consumption, and higher speeds [3]. - In 3D NAND, hybrid bonding is expected to replace some existing structures, enabling stable manufacturing at higher stacking layers (e.g., over 300 layers) [3][7]. - Leading companies like Micron, SK Hynix, and Samsung are actively investing in hybrid bonding technology for HBM4 and next-generation CUBE architectures, highlighting its strategic importance [3][5]. Group 2: Samsung's Initiatives - Samsung has shown a strong commitment to hybrid bonding, recognizing its necessity for manufacturing 16-layer HBM [4][5]. - The company plans to produce HBM4 samples by 2025, with mass production expected in 2026, and has already tested a 16-layer HBM sample using hybrid bonding technology [5][6]. - Samsung is also preparing for a custom HBM business, responding to demand from major tech companies like Google and NVIDIA for tailored HBM products [6][7]. Group 3: SK Hynix's Developments - SK Hynix is also pursuing hybrid bonding technology, planning to mass-produce 16-layer HBM4 by 2026 and exploring the potential for over 20 layers [9][10]. - The company aims to implement hybrid bonding for its NAND products, targeting 400-layer NAND flash production by 2025 [10][11]. Group 4: Micron's Position - Micron has been relatively quiet about hybrid bonding but has begun delivering HBM4 samples, which feature a capacity of 36 GB and a bandwidth of up to 2 TB/s [13][14]. - The company is focusing on optimizing existing technologies and may adopt hybrid bonding later than its competitors [14]. Group 5: Equipment Manufacturers - Equipment manufacturers like BESI and Applied Materials are leading the hybrid bonding equipment market, with BESI having developed systems for high-precision bonding since 2019 [15][16]. - Applied Materials has integrated its hybrid bonding platform with wafer processing data, emphasizing system-level integration [16][17]. - Other companies, including ASMPT and Korean firms like Hanmi Semiconductor and Hanwha, are also entering the hybrid bonding equipment market, with various development stages and partnerships [18][19][20]. Group 6: Future Outlook - The semiconductor industry is increasingly focused on hybrid bonding as a key technology to overcome traditional packaging limitations and achieve higher performance integration [25]. - As Moore's Law slows, hybrid bonding is expected to play an irreplaceable role in advancing the industry towards greater integration and performance [25].