芯粒多芯片集成封装服务
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马年IPO第一审!无锡“独角兽”成功过会
Xin Lang Cai Jing· 2026-02-26 10:25
(来源:上观新闻) 盛合晶微成立于2014年11月,是全球领先的集成电路晶圆级先进封测企业,起步于先进的12英寸中段硅 片加工,并进一步提供晶圆级封装(WLP)和芯粒多芯片集成封装等全流程的先进封测服务,致力于 支持各类高性能芯片,尤其是图形处理器(GPU)、中央处理器(CPU)、人工智能芯片等,通过超越 摩尔定律(More than Moore)的异构集成方式,实现高算力、高带宽、低功耗等的全面性能提升。 公司计划募集资金48亿元,用于三维多芯片集成封装项目和超高密度互联三维多芯片集成封装项目,通 过形成多个芯粒多芯片集成封装技术平台的规模产能,并补充配套的 Bumping 产能,提升公司科技创 新能力,实现核心技术的产业化,扩充产品组合,保证配套 Bumping 环节的产能供应,促进主营业务 的快速发展。 3、杭州提前入春!西湖龙井头采茶将有所提前 据气象信息,今年杭州入春比常年提早了半个月。 1、吴庆文专题调研沪苏(州)同城化工作 2月26日,苏州市委副书记、市长吴庆文到苏州工业园区和昆山市围绕深化沪苏(州)同城化工作开展 专题调研。他强调,要大力推动沪苏两地要素流动高效便捷、创新资源协同配置,以更高标 ...
马年首家IPO过会,盛合晶微拟募资48亿元
Sou Hu Cai Jing· 2026-02-25 10:14
业绩方面,2023年、2024年和2025年上半年,盛合晶微分别实现营业收入30.38亿元、47.05亿元和31.78 亿元,归母净利润分别为3413.06万元、2.14亿元和4.35亿元。 招股书显示,此次科创板IPO,盛合晶微拟募集资金48亿元,投向三维多芯片集成封装项目、超高密度 互联三维多芯片集成封装项目,拟重点打造芯粒多芯片集成封装技术平台的规模产能,并补充配套凸块 制造产能,加码3DIC等前沿封装技术的研发与产业化。 股权架构方面,最近两年内,盛合晶微无控股股东且无实际控制人。截至招股书签署日,盛合晶微第一 大股东无锡产发基金持股比例为10.89%,第二大股东招银系股东合计控制股权比例为9.95%,第三大股 东厚望系股东合计持股比例为6.76%。 2月24日,上交所官网显示,盛合晶微半导体有限公司(简称"盛合晶微")科创板IPO已通过上交所上市 审核委员会审议,成为马年首家科创板过会企业。 公开资料显示,盛合晶微是全球领先的集成电路晶圆级先进封测企业,起步于先进的12英寸中段硅片加 工,并进一步提供晶圆级封装和芯粒多芯片集成封装等全流程的先进封测服务。公司致力于支持各类高 性能芯片,尤其是GPU、 ...
上峰水泥参股公司盛合晶微科创板上市申请通过审议
Zhi Tong Cai Jing· 2026-02-24 10:11
Core Viewpoint - The company Shenghe Jingwei, in which the company holds a stake, has received approval for its initial public offering (IPO) and listing on the Sci-Tech Innovation Board [1] Group 1 - Shenghe Jingwei is an advanced packaging and testing enterprise for integrated circuits, starting with 12-inch mid-range silicon wafer processing [1] - The company provides a full range of advanced packaging and testing services, including wafer-level packaging (WLP) and chiplet multi-chip integration packaging [1]
上峰水泥(000672.SZ)参股公司盛合晶微科创板上市申请通过审议
智通财经网· 2026-02-24 10:10
Core Viewpoint - The company Shengtai Cement (000672.SZ) announced that its associate company, Shenghe Jingwei, has received approval for its initial public offering (IPO) and listing on the Sci-Tech Innovation Board [1] Group 1: Company Overview - Shenghe Jingwei is an advanced packaging and testing enterprise specializing in integrated circuit wafer-level packaging [1] - The company started with 12-inch mid-range silicon wafer processing and offers a full range of advanced packaging services, including wafer-level packaging (WLP) and chiplet multi-chip integrated packaging [1]
盛合晶微IPO无实控人,汪灿等6名董事与股东关联关系披露
Sou Hu Cai Jing· 2026-02-03 09:11
Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. has responded to the second round of IPO inquiry from the Sci-Tech Innovation Board, with CICC as the sponsor [2] Group 1: Company Structure and Shareholding - The company has no actual controller, and major shareholders holding more than 5% of shares, including Advpackaging, have committed to a 36-month lock-up period starting from the listing date, with a total lock-up ratio of 39.22% [2] - There are interconnections among several shareholders, such as Puhua Chuangyu, Puhua Zhixin, and Hua Capital, which can be traced back to three natural person shareholders: Liu Yue, Chen Datong, and Wu Haibin [2] Group 2: Board and Management Relationships - The board consists of 9 directors, with some directors having relationships with shareholders, including being appointed by relevant shareholders or holding more than 5% equity in related shareholders [4] - The company has confirmed that there are no undisclosed relationships between senior management and shareholders, aside from those already disclosed [4] Group 3: Director Backgrounds - The company provided a detailed table of directors and their relationships with shareholders, indicating various levels of involvement and shareholdings [5] - Notable positions include the Chairman and CEO, who holds 18.14% of the equity in the employee stock ownership platform, and other directors with similar ties to shareholder entities [5] Group 4: Business Overview - Shenghe Jingwei is an advanced packaging and testing enterprise in the integrated circuit industry, focusing on 12-inch silicon wafer processing and providing advanced packaging services such as wafer-level packaging (WLP) and multi-chip integration packaging [2] - The company aims to support high-performance chips, particularly GPUs, CPUs, and AI chips, by enhancing performance through heterogeneous integration beyond Moore's Law, achieving high computing power, high bandwidth, and low power consumption [2]