Core Insights - The article highlights the significant growth and developments in the advanced packaging and heterogeneous integration sectors of the semiconductor industry, driven by increasing demand from artificial intelligence and data centers [3]. Group 1: Industry Events and Trends - The SEMICON China exhibition showcased a strong focus on high-end semiconductor equipment, with both international and domestic manufacturers emphasizing their advancements in the advanced packaging sector [2]. - Major international companies like Canon, ASML, and SCREEN presented wafer-level and panel-level lithography equipment, while domestic leaders such as North Huachuang and Shengmei Shanghai displayed equipment for 2.5D/3D heterogeneous integration [2]. - The advanced packaging and heterogeneous integration industries are accelerating the global semiconductor market towards a valuation of $1 trillion [2]. Group 2: Market Statistics and Projections - According to TrendBank, the global advanced packaging market is projected to reach $59.2 billion by 2025, reflecting a growth rate of 25% [3]. - The panel-level packaging (PLP) market is expected to grow to $247 million by 2025, with a remarkable growth rate of 40% [3]. - The current demand for 2.5D/3D packaging in China is limited due to constraints in advanced wafer orders, indicating that the market has not yet reached a peak demand phase [3]. Group 3: Strategic Players - Key players in the 2.5D/3D and FOPLP sectors include companies like Tongfu Microelectronics, Huatian Technology, and Xiamen Yuntian, among others, each focusing on specific advanced packaging technologies [4].

Core Viewpoint - Yongxi Electronics has achieved significant breakthroughs in advanced packaging technology, focusing on AI computing and heterogeneous integration, positioning itself as a key player in the domestic high-end integrated circuit packaging and testing sector [3][7]. Group 1: Advanced Packaging Technology - Yongxi Electronics will showcase its full range of advanced packaging technology and mass production products at SEMICON China 2026, highlighting its latest breakthroughs in 2.5D/3D heterogeneous integration and AI computing chip FCBGA packaging [1][3]. - The FCBGA packaging product, specifically designed for AI computing chips, has achieved large-scale mass production and meets the stringent technical requirements for high-end CPUs, GPUs, and AI training chips [4][6]. Group 2: Heterogeneous Integration - Yongxi Electronics has completed the R&D and engineering implementation of 2.5D/3D heterogeneous integration technology, which is crucial for overcoming performance and cost limitations of single chips [5][7]. - The company has established a comprehensive service capability covering the entire packaging process, including bumping, chip probing, flip chip packaging, and final testing, creating a closed-loop system [5][6]. Group 3: Market Position and Future Plans - The company’s full-process capability allows chip design clients to achieve one-stop delivery from wafer to finished product, significantly reducing supply chain management costs and ensuring stable yield and delivery times [6][7]. - Yongxi Electronics plans to continue investing in the R&D and capacity expansion of advanced packaging technologies, aiming to enhance its competitiveness in both domestic and international markets [7].

Summary of Conference Call Records Industry Overview - The discussion revolves around the advancements in AI inference chips, specifically focusing on the roles of GPU, LPU, TPU, and NPU in the evolving landscape of AI processing and data centers [1][2][3]. Key Points and Arguments GPU and LPU Collaboration - GPUs are transitioning from being a replacement to a complementary role with LPUs, where GPUs excel in the prefill stage of large-scale parallel processing, while LPUs provide low-latency advantages in the decode stage, significantly improving P95/P99 tail latency [1][2]. - NVIDIA is expected to launch a rack-level integrated solution that combines 64 clusters of LPU and GPU, aiming to deliver high throughput and extremely low interaction latency [1][3]. LPU Technology and Limitations - The core technology supporting LPU is 3D stacking packaging, which vertically stacks on-chip SRAM/DRAM with computing cores to shorten access links, resulting in low access latency despite a capacity of only hundreds of megabytes [1][7]. - LPUs cannot replace Tensor Cores as they focus on language text processing and lack the parallel computing and graphics rendering capabilities necessary for training trillion-parameter models [1][4][5]. Heterogeneous Integration - Heterogeneous integration is becoming essential due to yield limitations at advanced process nodes like 2nm. Chiplets allow the integration of different CPUs, GPUs, and NPUs, effectively reducing TCO and enhancing system efficiency [1][3][9]. Power Consumption and Cooling Solutions - The power consumption of single chips is approaching 2000W, necessitating a shift in data centers from air cooling to cold plate or immersion cooling, along with upgrades to server power supply systems to match dynamic power scheduling [2][15][16]. LPU's Role in Inference - The inference process is divided into two stages: prefill and decode. The GPU handles the prefill stage, while the LPU takes over during the decode stage, which is sensitive to latency, thus improving user experience [6][11][12]. 3D Stacking and Packaging - 3D stacking enhances on-chip storage capabilities, allowing for lower latency and improved performance. This technology is already being applied in various sectors, including AI chips and consumer-grade chips [7][8][10]. Cost and Efficiency Optimization - Reducing inference costs involves replacing some general-purpose computing with dedicated computing, allowing for more efficient task allocation among different processing units [18]. Multi-modal Inference - There is currently no definitive chip that excels in multi-modal inference. Future developments may involve a combination of general-purpose and specialized chips to enhance efficiency in multi-modal tasks [19][20]. Other Important Insights - The integration of LPU into NVIDIA's product line could lead to significant advancements in AI processing, but the exact mechanisms and collaborative frameworks are still under development [17]. - The industry is witnessing a shift towards specialized chips like LPU due to the rising demand for dedicated processing power driven by the popularity of large language models [17]. This summary encapsulates the critical insights and developments discussed in the conference call, highlighting the evolving dynamics of AI chip technology and its implications for the industry.

Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. is advancing towards its IPO on the Sci-Tech Innovation Board, marking a significant step in its journey to become a publicly listed company [1] Company Overview - Shenghe Jingwei is a leading global provider of integrated circuit wafer-level advanced packaging and testing services, starting with advanced 12-inch mid-size silicon wafer processing [1] - The company offers a full range of advanced packaging services, including wafer-level packaging (WLP) and chiplet multi-chip integration packaging, aimed at supporting high-performance chips such as GPUs, CPUs, and AI chips [1] Technological Focus - The company is committed to enhancing performance through heterogeneous integration methods that exceed Moore's Law, achieving improvements in computing power, bandwidth, and energy efficiency [1] IPO Details - The IPO application was accepted on October 30, 2025, and was approved on February 24, 2026 [1] - Shenghe Jingwei plans to raise approximately 4.8 billion yuan through this IPO [1]

Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. has applied for IPO on the Shanghai Stock Exchange's Sci-Tech Innovation Board, aiming to raise 4.8 billion RMB, and is recognized as a leading advanced packaging and testing enterprise in the integrated circuit industry [1]. Group 1: Company Overview - Shenghe Jingwei specializes in advanced packaging and testing services, focusing on wafer-level packaging (WLP) and chiplet multi-chip integration packaging, particularly for high-performance chips like GPUs, CPUs, and AI chips [1][3]. - The company has established itself as one of the earliest and largest players in the chiplet multi-chip integration packaging sector in mainland China, with capabilities to compete with global leaders [1][3]. Group 2: Technological Advancements - In the mid-sized silicon wafer processing field, Shenghe Jingwei is one of the first companies in mainland China to achieve mass production of 12-inch bumping and is the first to offer 14nm advanced process bumping services, filling a gap in the high-end integrated circuit manufacturing supply chain [2]. - The company has achieved significant advancements in wafer-level chip packaging, including the development of 12-inch WLCSP and Low-K WLCSP, leading the market with a 31% share in 2024 [2]. Group 3: Market Position - In the chiplet multi-chip integration packaging domain, Shenghe Jingwei holds a dominant position with an 85% market share in 2.5D integration revenue in 2024, showcasing its advanced technology comparable to global leaders [3]. - The company provides customized advanced packaging services for various high-performance chips, catering to sectors such as AI, data centers, autonomous driving, and 5G communications, thus contributing to China's digital and intelligent infrastructure [3]. Group 4: Financial Performance - The company reported revenues of approximately 1.633 billion RMB, 3.038 billion RMB, and 4.705 billion RMB for the years 2022, 2023, and 2024 respectively, with a projected revenue of 3.178 billion RMB for the first half of 2025 [4]. - Net profits for the same periods were approximately -329 million RMB, 34.13 million RMB, 214 million RMB, and 435 million RMB for the first half of 2025 [4].

Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. has successfully passed the listing review by the Shanghai Stock Exchange for its IPO on the Sci-Tech Innovation Board, becoming the first company to be approved in the Year of the Rabbit [1] Group 1: Company Overview - Shenghe Jingwei is a leading global advanced packaging and testing enterprise for integrated circuits, specializing in advanced 12-inch silicon wafer processing and providing full-process advanced packaging services [1] - The company focuses on supporting high-performance chips, particularly GPUs, CPUs, and AI chips, aiming to enhance performance through heterogeneous integration that surpasses Moore's Law, achieving high computing power, high bandwidth, and low power consumption [1] Group 2: Financial Performance - For the years 2023, 2024, and the first half of 2025, Shenghe Jingwei is projected to achieve operating revenues of 3.038 billion yuan, 4.705 billion yuan, and 3.178 billion yuan, respectively, with net profits attributable to the parent company of 34.13 million yuan, 214 million yuan, and 435 million yuan [1] Group 3: IPO Details - The company plans to raise 4.8 billion yuan through its IPO, which will be allocated to projects including three-dimensional multi-chip integration packaging and ultra-high-density interconnect three-dimensional multi-chip integration packaging, focusing on scaling the chiplet multi-chip integration packaging technology platform and enhancing bump manufacturing capacity [1] Group 4: Shareholding Structure - In the past two years, Shenghe Jingwei has had no controlling shareholder or actual controller. As of the signing date of the prospectus, the largest shareholder, Wuxi Industrial Development Fund, holds a 10.89% stake, while the second largest shareholder, the Zhuhai Bank system, controls 9.95%, and the third largest shareholder, the Houwang system, holds 6.76% [2]

Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. has successfully passed the IPO review on the Sci-Tech Innovation Board, marking it as the first IPO of the Year of the Horse [1] Company Overview - Shenghe Jingwei is an advanced packaging and testing enterprise for integrated circuit wafers, starting with advanced 12-inch silicon wafer processing [1] - The company provides a full range of advanced packaging and testing services, including wafer-level packaging (WLP) and chiplet multi-chip integration packaging [1] - The focus is on supporting high-performance chips, particularly graphics processing units (GPUs), central processing units (CPUs), and artificial intelligence chips, aiming for performance improvements in computing power, bandwidth, and energy efficiency through heterogeneous integration beyond Moore's Law [1] IPO Details - The IPO was accepted on October 30, 2025, and entered the inquiry stage on November 14 of the same year [1] - Shenghe Jingwei aims to raise 4.8 billion yuan through this IPO [1] Technical and Market Considerations - During the listing committee meeting, Shenghe Jingwei was asked to explain the technical sources of its 2.5D business, the application fields and development trends of three technical routes, market space, and the situation of new customer development [1] - The company was also required to clarify the stability of its business with major clients and the sustainability of its performance [1]

Core Viewpoint - The article emphasizes the importance of heterogeneous integration and optoelectronic fusion in the semiconductor and optoelectronic industries as key paths for technological breakthroughs and domestic substitution, especially with the rapid growth of AI computing power and the upcoming 5G-A and 6G deployments [1]. Industry Overview - By 2025, China's semiconductor market is projected to exceed 2.3 trillion yuan, with the optoelectronic device market accounting for 18%. However, the domestic substitution rate in critical areas such as third-generation semiconductor materials, high-end EDA tools, and photonic integrated chips (PIC) remains below 40% [1]. - The upcoming "Collaborative Innovation Forum from Devices to Networks" aims to facilitate collaboration across the entire industry chain, bringing together key players from academia, enterprises, and demand-side [1]. Event Details - The forum will take place on March 18, 2026, at the Shanghai New International Expo Center, focusing on full industry chain collaboration [1]. - The event will gather around 200 core industry practitioners, including major telecom operators, leading cloud service providers, equipment manufacturers, and key players in the optoelectronic and semiconductor sectors [1]. Participation and Engagement - The forum will also feature a live broadcast on the Semiconductor Industry Observation video account, expected to attract over 100,000 industry peers, breaking down geographical barriers for communication [2]. - Notably, 45% of participating companies have revenues exceeding 1 billion yuan, with an average of over 15% of their revenue invested in R&D [2]. Technological Breakthroughs - The article highlights that the domestic semiconductor industry's breakthroughs are not isolated but require a full-chain collaboration from materials to applications. Current advancements in areas like advanced packaging and optical matrix computing (oMAC) have established a foundation for collaboration [2]. - The event's agenda includes discussions on various topics, such as optoelectronic integrated chips for information and communication systems, silicon photonics for high-speed AI optical connections, and the advantages of silicon capacitors in AI applications [3][4]. Collaborative Innovation - The core of collaborative innovation is to break down information barriers and technological silos, allowing for rapid transformation of academic research into industrial productivity and driving technological iterations through enterprise application needs [7]. - The forum aims to create a bridge for efficient connections across the entire chain from source innovation to industrial implementation, facilitating direct procurement opportunities for participating companies with major cloud service providers and telecom operators [6][7].

Core Viewpoint - The article discusses the advancements in UCIe 3.0, particularly its increased data rates and improved management features, which are crucial for meeting the growing demands of artificial intelligence workloads in data centers [2][3]. Group 1: UCIe 3.0 Features - UCIe 3.0 doubles the maximum allowed data rate for UCIe-S and UCIe-A from 32 GT/s to 64 GT/s, with 48 GT/s also mentioned [5]. - The new version introduces better management capabilities, allowing for more efficient firmware distribution across multiple Chiplets [10]. - UCIe 3.0 enhances streaming transmission and recalibration functions, addressing previously unresolved issues [15][20]. Group 2: Technical Improvements - The use of quarter-rate signaling enables higher data rates of 48 GT/s and 64 GT/s, significantly reducing risks for users and vendors in creating new intellectual property [6][7]. - The error rates for 48 GT/s and 64 GT/s are acceptable at 10¹⁵ and 10¹² respectively, especially when considering CRC checks and replay mechanisms [6]. - Power consumption remains below 0.5 pJ/bit at lower data rates, with higher rates targeting 0.75 pJ/bit [7]. Group 3: System Design and Integration Challenges - The increasing complexity of heterogeneous integration poses new challenges, including rising power and thermal demands, as well as system-level verification across stacked architectures [9]. - As UCIe moves to 64 Gbps, design margins shrink, increasing wiring density and signal integrity risks [9]. Group 4: Compatibility and Adoption - UCIe 3.0 maintains compatibility with previous versions, allowing for new bandwidth without changing bump locations [8][21]. - The industry is shifting towards UCIe standards, with many previously using custom solutions now considering UCIe due to its advancements [21].

Core Insights - The introduction of 2nm and more advanced process nodes will require new power consumption and thermal management methods, while also providing greater design flexibility and more options for performance enhancement and cost optimization [2] - The semiconductor market is evolving, with a shift from traditional low-power chips for mobile devices and high-performance chips for servers to more specialized applications driven by artificial intelligence [2][3] - The transition to multi-die components allows for prioritization of different processors and functionalities, simplifying emergency plans during component shortages [2][3] Group 1: Design and Manufacturing Challenges - The complexity of integrating various components in chipsets is significant, as designing and manufacturing chipsets is easier than integrating them [4] - A hybrid design approach allows for the combination of different standard cells, enhancing flexibility and performance while managing power consumption [5] - The interconnect technology between chips has improved, allowing for the mixing of different process nodes, which helps mitigate cost and yield challenges [6] Group 2: Performance and Power Management - The performance and power advantages of new nodes are not absolute; the real value lies in how close the system can approach the physical limits of silicon [7] - The economic benefits of 2nm technology depend on intelligent management of the power band, as excessive power bands can lead to wasted investments [7] - The trend of increasing power density with each new node presents challenges in thermal management, necessitating advanced cooling solutions [11][12] Group 3: Market Dynamics and Future Directions - The reasons for upgrading to higher process nodes are no longer based on a single factor but vary by market segment and workload [15] - The integration of multiple nodes in a single design is becoming more common, with new PPA/C trade-offs to balance priorities in large systems [15] - The semiconductor industry is at a turning point, requiring continuous management of correctness rather than assuming everything is normal at acceptance [10]