北京商报讯（记者 王蔓蕾）2月25日晚间，上交所官网显示，盛合晶微半导体有限公司（以下简称"盛 合晶微"）科创板IPO提交注册，公司冲击上市进入最后一关。 本次冲击上市，盛合晶微拟募集资金约48亿元。 据了解，盛合晶微是全球领先的集成电路晶圆级先进封测企业，起步于先进的12英寸中段硅片加工，并 进一步提供晶圆级封装（WLP）和芯粒多芯片集成封装等全流程的先进封测服务，致力于支持各类高 性能芯片，尤其是图形处理器（GPU）、中央处理器（CPU）、人工智能芯片等，通过超越摩尔定律 （More than Moore）的异构集成方式，实现高算力、高带宽、低功耗等的全面性能提升。公司IPO于 2025年10月30日获得受理，2026年2月24日上会获得通过。 ...

| 项目 | 2025年1-6月 /2025年6月30日 | 12月31日 | 2024年度/2024年 2023年度/2023年 2022年度/2022年 12月 31 日 | 12月 31 日 | | --- | --- | --- | --- | --- | | 资产总额(万元) | 2.141.711.96 | 2,033,200.79 | 1,273,379.19 | 652,254.76 | | 归属于母公司所有者权益 (万元) | 1.408.879.11 | 1.359.149.28 | 797.934.48 | 381,551.14 | | 资产负债率(母公司) | 0.08% | 0.06% | 0.00% | 0.36% | | 营业收入(万元) | 317,799.62 | 470.539.56 | 303.825.98 | 163.261.51 | | 净利润(万元) | 43.489.45 | 21.365.32 | 3.413.06 | -32.857.12 | 在晶圆级封装领域，基于领先的中段硅片加工能力，公司快速实现了12英寸大尺寸晶圆级芯片封装(晶圆级 扇入型封装，WLCS ...

业绩方面，2023年、2024年和2025年上半年，盛合晶微分别实现营业收入30.38亿元、47.05亿元和31.78 亿元，归母净利润分别为3413.06万元、2.14亿元和4.35亿元。 招股书显示，此次科创板IPO，盛合晶微拟募集资金48亿元，投向三维多芯片集成封装项目、超高密度 互联三维多芯片集成封装项目，拟重点打造芯粒多芯片集成封装技术平台的规模产能，并补充配套凸块 制造产能，加码3DIC等前沿封装技术的研发与产业化。 股权架构方面，最近两年内，盛合晶微无控股股东且无实际控制人。截至招股书签署日，盛合晶微第一 大股东无锡产发基金持股比例为10.89%，第二大股东招银系股东合计控制股权比例为9.95%，第三大股 东厚望系股东合计持股比例为6.76%。 2月24日，上交所官网显示，盛合晶微半导体有限公司（简称"盛合晶微"）科创板IPO已通过上交所上市 审核委员会审议，成为马年首家科创板过会企业。 公开资料显示，盛合晶微是全球领先的集成电路晶圆级先进封测企业，起步于先进的12英寸中段硅片加 工，并进一步提供晶圆级封装和芯粒多芯片集成封装等全流程的先进封测服务。公司致力于支持各类高 性能芯片，尤其是GPU、 ...

北京商报讯2月24日晚间，上交所官网显示，盛合晶微半导体有限公司（以下简称"盛合晶微"）科创板 IPO当日上会获得通过，这也是马年首家IPO上会企业。 据了解，盛合晶微是一家集成电路晶圆级先进封测企业，起步于先进的12英寸中段硅片加工，并进一步 提供晶圆级封装（WLP）和芯粒多芯片集成封装等全流程的先进封测服务，致力于支持各类高性能芯 片，尤其是图形处理器（GPU）、中央处理器（CPU）、人工智能芯片等，通过超越摩尔定律（More than Moore）的异构集成方式，实现高算力、高带宽、低功耗等的全面性能提升。公司IPO于2025年10 月30日获得受理，当年11月14日进入问询阶段。本次冲击上市，盛合晶微拟募集资金48亿元。 在上市委会议现场，上市委要求盛合晶微结合公司2.5D业务的技术来源，三种技术路线的应用领域、发 展趋势、市场空间，以及新客户开拓情况，说明与主要客户的业务稳定性及业绩可持续性。 （文章来源：北京商报） ...

Core Viewpoint - The article emphasizes the importance of heterogeneous integration and optoelectronic fusion in the semiconductor and optoelectronic industries as key paths for technological breakthroughs and domestic substitution, especially with the rapid growth of AI computing power and the upcoming 5G-A and 6G deployments [1]. Industry Overview - By 2025, China's semiconductor market is projected to exceed 2.3 trillion yuan, with the optoelectronic device market accounting for 18%. However, the domestic substitution rate in critical areas such as third-generation semiconductor materials, high-end EDA tools, and photonic integrated chips (PIC) remains below 40% [1]. - The upcoming "Collaborative Innovation Forum from Devices to Networks" aims to facilitate collaboration across the entire industry chain, bringing together key players from academia, enterprises, and demand-side [1]. Event Details - The forum will take place on March 18, 2026, at the Shanghai New International Expo Center, focusing on full industry chain collaboration [1]. - The event will gather around 200 core industry practitioners, including major telecom operators, leading cloud service providers, equipment manufacturers, and key players in the optoelectronic and semiconductor sectors [1]. Participation and Engagement - The forum will also feature a live broadcast on the Semiconductor Industry Observation video account, expected to attract over 100,000 industry peers, breaking down geographical barriers for communication [2]. - Notably, 45% of participating companies have revenues exceeding 1 billion yuan, with an average of over 15% of their revenue invested in R&D [2]. Technological Breakthroughs - The article highlights that the domestic semiconductor industry's breakthroughs are not isolated but require a full-chain collaboration from materials to applications. Current advancements in areas like advanced packaging and optical matrix computing (oMAC) have established a foundation for collaboration [2]. - The event's agenda includes discussions on various topics, such as optoelectronic integrated chips for information and communication systems, silicon photonics for high-speed AI optical connections, and the advantages of silicon capacitors in AI applications [3][4]. Collaborative Innovation - The core of collaborative innovation is to break down information barriers and technological silos, allowing for rapid transformation of academic research into industrial productivity and driving technological iterations through enterprise application needs [7]. - The forum aims to create a bridge for efficient connections across the entire chain from source innovation to industrial implementation, facilitating direct procurement opportunities for participating companies with major cloud service providers and telecom operators [6][7].

Core Viewpoint - The article discusses the advancements in UCIe 3.0, particularly its increased data rates and improved management features, which are crucial for meeting the growing demands of artificial intelligence workloads in data centers [2][3]. Group 1: UCIe 3.0 Features - UCIe 3.0 doubles the maximum allowed data rate for UCIe-S and UCIe-A from 32 GT/s to 64 GT/s, with 48 GT/s also mentioned [5]. - The new version introduces better management capabilities, allowing for more efficient firmware distribution across multiple Chiplets [10]. - UCIe 3.0 enhances streaming transmission and recalibration functions, addressing previously unresolved issues [15][20]. Group 2: Technical Improvements - The use of quarter-rate signaling enables higher data rates of 48 GT/s and 64 GT/s, significantly reducing risks for users and vendors in creating new intellectual property [6][7]. - The error rates for 48 GT/s and 64 GT/s are acceptable at 10¹⁵ and 10¹² respectively, especially when considering CRC checks and replay mechanisms [6]. - Power consumption remains below 0.5 pJ/bit at lower data rates, with higher rates targeting 0.75 pJ/bit [7]. Group 3: System Design and Integration Challenges - The increasing complexity of heterogeneous integration poses new challenges, including rising power and thermal demands, as well as system-level verification across stacked architectures [9]. - As UCIe moves to 64 Gbps, design margins shrink, increasing wiring density and signal integrity risks [9]. Group 4: Compatibility and Adoption - UCIe 3.0 maintains compatibility with previous versions, allowing for new bandwidth without changing bump locations [8][21]. - The industry is shifting towards UCIe standards, with many previously using custom solutions now considering UCIe due to its advancements [21].

Core Insights - The introduction of 2nm and more advanced process nodes will require new power consumption and thermal management methods, while also providing greater design flexibility and more options for performance enhancement and cost optimization [2] - The semiconductor market is evolving, with a shift from traditional low-power chips for mobile devices and high-performance chips for servers to more specialized applications driven by artificial intelligence [2][3] - The transition to multi-die components allows for prioritization of different processors and functionalities, simplifying emergency plans during component shortages [2][3] Group 1: Design and Manufacturing Challenges - The complexity of integrating various components in chipsets is significant, as designing and manufacturing chipsets is easier than integrating them [4] - A hybrid design approach allows for the combination of different standard cells, enhancing flexibility and performance while managing power consumption [5] - The interconnect technology between chips has improved, allowing for the mixing of different process nodes, which helps mitigate cost and yield challenges [6] Group 2: Performance and Power Management - The performance and power advantages of new nodes are not absolute; the real value lies in how close the system can approach the physical limits of silicon [7] - The economic benefits of 2nm technology depend on intelligent management of the power band, as excessive power bands can lead to wasted investments [7] - The trend of increasing power density with each new node presents challenges in thermal management, necessitating advanced cooling solutions [11][12] Group 3: Market Dynamics and Future Directions - The reasons for upgrading to higher process nodes are no longer based on a single factor but vary by market segment and workload [15] - The integration of multiple nodes in a single design is becoming more common, with new PPA/C trade-offs to balance priorities in large systems [15] - The semiconductor industry is at a turning point, requiring continuous management of correctness rather than assuming everything is normal at acceptance [10]

Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. has responded to the second round of IPO inquiry from the Sci-Tech Innovation Board, with CICC as the sponsor [2] Group 1: Company Structure and Shareholding - The company has no actual controller, and major shareholders holding more than 5% of shares, including Advpackaging, have committed to a 36-month lock-up period starting from the listing date, with a total lock-up ratio of 39.22% [2] - There are interconnections among several shareholders, such as Puhua Chuangyu, Puhua Zhixin, and Hua Capital, which can be traced back to three natural person shareholders: Liu Yue, Chen Datong, and Wu Haibin [2] Group 2: Board and Management Relationships - The board consists of 9 directors, with some directors having relationships with shareholders, including being appointed by relevant shareholders or holding more than 5% equity in related shareholders [4] - The company has confirmed that there are no undisclosed relationships between senior management and shareholders, aside from those already disclosed [4] Group 3: Director Backgrounds - The company provided a detailed table of directors and their relationships with shareholders, indicating various levels of involvement and shareholdings [5] - Notable positions include the Chairman and CEO, who holds 18.14% of the equity in the employee stock ownership platform, and other directors with similar ties to shareholder entities [5] Group 4: Business Overview - Shenghe Jingwei is an advanced packaging and testing enterprise in the integrated circuit industry, focusing on 12-inch silicon wafer processing and providing advanced packaging services such as wafer-level packaging (WLP) and multi-chip integration packaging [2] - The company aims to support high-performance chips, particularly GPUs, CPUs, and AI chips, by enhancing performance through heterogeneous integration beyond Moore's Law, achieving high computing power, high bandwidth, and low power consumption [2]

Core Insights - The semiconductor industry is shifting focus from process technology to advanced packaging as AI chip demand surges and high bandwidth memory (HBM) becomes more prevalent [2][4] - Gartner predicts a 21% growth in the global semiconductor market by 2025, reaching approximately $793.45 billion, with advanced packaging technology becoming a key growth driver [2] - Major players like TSMC, Intel, and Samsung are intensifying their R&D and investments in advanced packaging, leading to heightened competition [2][4] TSMC's Innovations - TSMC's WMCM (Wafer-Level Multi-Chip Module) technology is set to revolutionize packaging for Apple's A20 chip, with mass production expected by the end of 2026 [3] - WMCM integrates memory with CPU, GPU, and NPU on a single wafer, significantly improving signal transmission and thermal performance while reducing costs [3][4] Intel's Strategy - Intel is showcasing its glass substrate technology combined with EMIB (Embedded Multi-Die Interconnect Bridge), aiming to redefine multi-chip interconnect rules [5][9] - The new packaging sample features a large size and advanced stacking architecture, addressing bandwidth limitations for AI accelerators and high-performance computing [5][8] Samsung's Approach - Samsung is focusing on thermal management innovations with its Heat Pass Block (HPB) technology, enhancing heat dissipation in mobile SoCs [10][12] - HPB technology reduces thermal resistance by 16% and lowers chip operating temperatures by 30%, addressing performance throttling in high-load scenarios [12][13] Advanced Packaging Market Trends - The advanced packaging market is characterized by multiple competing technologies, with 2.5D/3D packaging expected to see a compound annual growth rate of 23% from 2023 to 2029 [15] - TSMC's CoWoS capacity is projected to double by 2026, primarily serving major clients like NVIDIA [15][17] Future Directions - Material innovation is crucial for advanced packaging, with glass substrates emerging as a viable alternative to organic substrates due to their superior thermal stability and wiring density [29][30] - Heterogeneous integration is becoming mainstream, allowing for the combination of different chip types within a single package, enhancing performance and efficiency [31][32] - Thermal management is evolving to address the increasing power density of chips, with solutions like HPB setting new benchmarks for packaging-level heat management [33] - Photonic-electronic integration (CPO) is anticipated to revolutionize data transmission, addressing bandwidth and power consumption challenges in data centers [34]

Core Insights - TSMC has raised its 2026 capital expenditure to $52-56 billion, with 10-20% allocated to advanced packaging, indicating a high growth cycle driven by AI chip demand [1] - The advanced packaging market is expected to grow at a CAGR of 8.9% from 2019 to 2029, increasing its share from 45.6% to 50.9%, surpassing traditional packaging [1] Industry Trends - Technological advancements focus on enhancing electrical performance, integration, thermal management, and cost reduction, with key enabling technologies including Bump, RDL, Wafer-level packaging, and TSV [3] - Current trends include 2.5D/3D packaging and Chiplet technology, which offer significant advantages in yield improvement, cost reduction, and compatibility across multiple processes [3] Market Dynamics - Advanced packaging addresses multiple bottlenecks in the post-Moore's Law era, such as alleviating the "memory wall" with 2.5D/3D integration of high bandwidth memory, breaking the "area wall" through multi-chip stacking, and optimizing power consumption and heat dissipation to tackle the "power wall" [5] - The global packaging revenue is dominated by Taiwan (43.7%), the USA (21%), and mainland China (20.2%), with mainland China's advanced packaging share at approximately 15.5% [7] Growth Projections - The advanced packaging market in mainland China is projected to grow from 51.4 billion yuan in 2024 to 100.6 billion yuan in 2029, with a CAGR of 14.4% [7] - The global advanced packaging market is expected to reach approximately $45 billion in 2024, accounting for 55% of the packaging market, and is projected to grow to $80 billion by 2030, with a CAGR of 9.4% from 2024 to 2030 [7] Company Developments - Changdian Technology has launched the XDFOI® chip integration process and has begun mass production [8] - Tongfu Microelectronics plans to expand production through a private placement, with a 55.7% increase in net profit for the first three quarters of 2025 [8] - Huada Semiconductor has acquired Huayi Microelectronics to expand its power device packaging and has established a subsidiary to enhance 2.5D/3D advanced packaging [8] - Yongxi Electronics is leveraging the FH-BSAP platform to meet diverse advanced packaging needs, with expected revenue of 4.2-4.6 billion yuan in 2025 [8]