Core Viewpoint - The company reported its 2024 annual results and Q1 2025 results, showing a significant increase in revenue but a decline in net profit due to increased R&D expenses and a shift to a loss in non-recurring profit [1][2]. Financial Performance - In 2024, the company achieved total revenue of 1.222 billion, a year-on-year increase of 20.98% - The net profit attributable to shareholders was 109 million, a year-on-year decrease of 45.46% - The non-recurring net profit was -57 million, compared to 64 million in the same period last year, indicating a shift from profit to loss - In Q1 2025, total revenue was 234 million, a year-on-year increase of 9.77% - The net profit attributable to shareholders was 10 million, a year-on-year increase of 26.72% [1]. R&D Investment - The company increased its R&D investment in 2024, with R&D expenses reaching 868 million, a year-on-year increase of 26.77% - The R&D expense ratio was 71.02%, up by 3.25 percentage points, marking a historical high - The number of R&D personnel reached 914, an increase of 18.1% year-on-year, reflecting the talent-intensive nature of the EDA industry [1][2]. Product Development - The company upgraded its traditional product lines, launching several new tools: - The Andes design automation platform, including Andes Analog for analog circuits and Andes Power for power transistors - The AetherLE layout editing tool with a new coloring function for different mask layers - The ALPS RF circuit simulation tool, reducing simulation time from 1-2 weeks to under 8 hours - The Optimus tool for optical proximity effect optimization in flat panel displays [2]. Strategic Initiatives - The company is accelerating its layout in wafer manufacturing and advanced packaging: - Development of the Layout Decomposer for high-performance mask layout splitting - Introduction of the Vision platform for process diagnostics to improve yield - New tools for 3DIC, including Aether 3DIC and Argus 3DStack - The acquisition of Chip and Semiconductor on March 17, 2025, aims to enhance the company's capabilities in 3DIC Chiplet and RF circuit EDA products, positioning it as a global EDA leader [3]. Future Outlook - The company maintains an "overweight" rating and has added profit forecasts for 2027 - The semiconductor industry's domestic production is seen as an inevitable trend, with the company expected to grow through both organic growth and acquisitions - Projected revenues for 2025, 2026, and 2027 are 1.62 billion, 2.06 billion, and 2.65 billion respectively, with net profits of 250 million, 410 million, and 600 million respectively [4].

以下文章来源于IC后摩院 ，作者赵瑜斌 IC后摩院 . 产业为天，学术为地，搬运在这天地间 如果您希望可以时常见面，欢迎标星收藏哦~ | Contents | | | --- | --- | | 引 | | | 01 | 架构设计 | | 02 | 设计实现 | | 03 | 仿真 | | 04 | PV验证/签核 | | 05 | 供电 / 功耗 | | 06 | 标准/底座/生态 | | 07 | 商用工具现状 | 本篇主要分享从设计视角，对于Chiplet tool的真实需求。在开始前，我们略去了Chiplet设计的必要性和 后摩路径的好处（在其他篇中我们再分享），但是我们从一个基本的角度来看必须用Chiplet来构建未来系 统，尤其是算力系统的必要性——晶体管transistor的增长。 上个月底参加了HiPi联盟大会，以及在近期多场和3DIC、先进封装有关的会议中，国内设计界对EDA的呼声 可谓此起彼伏。这几天方得空整理了一下若干专家对此的讨论和分享。由于流程环节繁多，内容庞大，本文仅 挑一些要点做分享，如有更适合的场合再分别做详细介绍。 2024年，成功商用单片（苹果M3 max@3nm）晶体管最 ...