Core Insights - Synopsys, Inc. is enhancing its role in semiconductor design through an expanded collaboration with Taiwan Semiconductor Manufacturing Company (TSMC) to meet the increasing demand for high-performance AI and system-on-chip (SoC) technologies [1][5] Collaboration with TSMC - Synopsys has certified its digital and analog design flows on TSMC's N2P and A16 processes, utilizing the NanoFlex architecture to optimize chip performance, reduce power consumption, and accelerate time-to-market [2][10] - The IC Validator certification for TSMC A16 improves physical verification, facilitating faster and more reliable design sign-offs [2] - The 3DIC Compiler platform supports advanced 3D stacking and CoWoS packaging technologies, contributing to multiple customer tape-outs and enhancing productivity for complex multi-die designs [3][10] - Synopsys is also collaborating with TSMC on silicon photonics, utilizing AI-optimized photonic flow to address performance and thermal challenges in AI systems [3] Comprehensive IP Portfolio - Synopsys' extensive IP portfolio supports leading standards such as PCIe 7.0, UCIe, HBM4, and 1.6T Ethernet, with dedicated automotive IP for TSMC's N5A and N3A nodes targeting key markets like AI, automotive, and high-performance computing [4] Strategic Partnerships - In addition to TSMC, Synopsys has formed strong partnerships with Intel Corporation and Arm Holdings to advance chip design and innovation [6][9] - The collaboration with Intel focuses on enabling design flows and IP solutions for Intel's latest 18A process node, optimizing performance, power, and area for next-generation processors [7] - Synopsys provides EDA tools and a broad IP portfolio compatible with Arm's CPU, GPU, and AI cores, ensuring quick integration of components and meeting power and performance targets [8][9] Industry Positioning - The strengthened collaboration with TSMC reinforces Synopsys' position as a critical partner in advanced chip development, well-positioned to drive long-term growth in the AI and multi-die era [5]

Core Insights - Synopsys, Inc. is collaborating closely with TSMC to deliver advanced EDA and IP products that support TSMC's leading-edge processes and packaging technologies, particularly in AI chip and multi-die design [2][3] - The partnership has resulted in multiple customer tape-outs, showcasing the effectiveness of the 3DIC Compiler platform and the comprehensive IP portfolio optimized for TSMC's advanced technologies [2][3] Collaboration and Innovation - Synopsys has made certified digital and analog flows available on TSMC's N2P and A16 processes, utilizing TSMC NanoFlex architecture to optimize performance and power [3][4] - The collaboration includes robust automotive IP solutions for TSMC N5A and N3A processes, ensuring high safety, security, and reliability while maximizing performance [3][4] Technology Advancements - The 3DIC Compiler platform supports advanced 3D stacking and CoWoS packaging technologies, enabling multiple customer tape-outs and enhancing productivity [6][7] - An AI-optimized photonic flow for TSMC-COUPE technology has been developed to improve system performance and address multi-wavelength and thermal requirements [7][8] IP Portfolio and Market Impact - Synopsys offers the industry's broadest IP portfolio optimized for low power on TSMC N2/N2P processes, which accelerates the path to silicon success and reduces integration risk [4][8] - The IP portfolio supports high-performance standards, including HBM4, 1.6T Ethernet, UCIe, PCIe 7.0, and UALink, catering to automotive, IoT, and HPC applications [8] Verification and Design Flow - Synopsys IC Validator signoff physical verification solution is certified for TSMC A16 process, enhancing DRC and LVS checking capabilities [5] - Ongoing collaboration on design flow development for TSMC's A14 process is expected to yield its first process design kit release in late 2025 [3][5]

Global EDA Industry Performance - The global EDA industry is projected to grow by 11% year-on-year in Q4 2024, reaching $4.9 billion, despite a weak performance in the Chinese market [3][4] - The EDA software industry is characterized by high technical barriers, talent reserves, user collaboration, and significant capital scale, with a market concentration exceeding 70% among the top three companies: Cadence, Synopsys, and Siemens EDA [5] Growth Drivers in EDA - The increasing demand for edge computing and high-performance computing (HPC) chips is driving the need for more complex and automated EDA solutions [6] - The rise of cloud solutions facilitates seamless collaboration and enhances accessibility for global design teams [6] - The integration of AI and machine learning algorithms into workflows is optimizing design accuracy and efficiency, reducing costly errors, and accelerating time-to-market [6] Segment Performance - CAE (Computer-Aided Engineering) revenue grew by 10.9% to $1.6969 billion [7] - IC physical design and verification saw a 15.4% increase, reaching $797.9 million [7] - PCB & MCM (Printed Circuit Board & Multi-Chip Module) revenue increased by 15.9% to $476.2 million [7] - Semiconductor IP (SIP) revenue grew by 7.9% to $1.7607 billion, with some companies reporting declines [7] - Service revenue increased by 11% to $195.6 million, reflecting strong design demand amid talent shortages [7] - IC packaging design revenue surged by 70%, indicating a significant rise in advanced packaging demand [7] AI's Role in EDA - EDA vendors are leveraging AI to optimize software engines, processes, and workflows, which is crucial for scalable and reliable outcomes [8] - AI applications in EDA include automating repetitive tasks, enhancing design optimization, and providing intelligent assistance through generative AI [11][12] - AI-driven tools can significantly reduce design cycles and improve accuracy, as demonstrated by Synopsys' AI-driven EDA tools [11] Future Outlook - The emergence of Chiplet technology is transforming chip design and manufacturing paradigms, necessitating new tool support for architecture exploration and signal integrity analysis [13] - EDA tools must evolve to support heterogeneous integration design, with companies like Synopsys and Cadence developing specialized tool suites for Chiplet design [13][15] - The collaboration between EDA tools and IP design capabilities will be critical for future competitiveness, as traditional IP markets face saturation [14]

Core Insights - Synopsys and Intel Foundry have announced collaborations to enhance EDA and IP solutions for advanced semiconductor processes, specifically targeting the Intel 18A and 18A-P process nodes [2][5][6] EDA and IP Solutions - Synopsys has introduced certified AI-driven digital and analog design flows for the Intel 18A process node and production-ready EDA flows for the Intel 18A-P process node, which includes advanced technologies like RibbonFET and PowerVia [2][6] - The collaboration aims to accelerate the development of AI and high-performance computing (HPC) chip designs, providing comprehensive technologies for mutual customers [5][6] Multi-Die Design Innovation - Synopsys and Intel Foundry are working together to enable the new Embedded Multi-die Interconnect Bridge-T (EMIB-T) technology, which combines benefits from both 2.5D and 3D packaging technologies [3][9] - The EMIB-T reference flow is powered by Synopsys' unified exploration-to-signoff platform, facilitating efficient designs and high-quality results [9] Power, Performance, and Area (PPA) Optimization - Synopsys' EDA flows are optimized for power and area, leveraging Intel's PowerVia technology for enhanced thermal-aware implementations [6][10] - The collaboration has resulted in significant advancements in power, performance, and area (PPA) for designs on Intel 18A and Intel 18A-P process nodes [6][10] Ecosystem Expansion - Synopsys has joined the Intel Foundry Accelerator Design Services Alliance and the Intel Foundry Accelerator Chiplet Alliance to further support the semiconductor ecosystem [11] - This membership aims to enhance interoperability and manufacturability for multi-die chip designs on Intel 18A [11]

Core Insights - Synopsys, in collaboration with TSMC, is enhancing EDA and IP solutions for advanced semiconductor designs, particularly focusing on AI chip design and 3D multi-die innovations [2][3] - The partnership aims to accelerate the adoption of Angstrom-scale designs through certified EDA flows on TSMC's latest processes, including A16 and N2P [2][4] Collaboration and Innovation - Synopsys and TSMC are working together to provide certified digital and analog flows that improve design productivity and optimization for advanced semiconductor processes [2][3] - The collaboration includes the development of EDA flows for TSMC's A14 process, demonstrating Synopsys' commitment to high-performance design solutions [5] Technology Advancements - Synopsys' 3DIC Compiler supports TSMC's CoWoS technology, enabling unprecedented 5.5x reticle interposer sizes, which is crucial for next-generation HPC and AI chips [7] - The integration of multi-physics analysis and signoff solutions with Ansys simulation technologies enhances power, thermal, and signal integrity analysis for advanced designs [7] IP Solutions and Market Impact - Synopsys offers a broad portfolio of silicon-proven IP solutions for TSMC's advanced processes, which are essential for achieving low power and high performance in various applications, including HPC and automotive [8][9] - The successful deployment of Synopsys IP in thousands of designs helps reduce integration risk while meeting stringent power, performance, and area targets [8] Industry Engagement - Synopsys is actively participating in industry events, such as the TSMC Tech Symposium, to showcase its innovations and strengthen partnerships within the semiconductor ecosystem [10]