EDA：芯片设计的 "隐形大脑"，AI 与国产替代如何改写格局？ 汉鼎智库咨询 2026-03-18 当一颗 3nm 制程芯片在晶圆厂完成量产，很少有人会想到，其从概念到 实物的过程中，藏着 EDA（电子设计自动化）工具的 "全流程操盘"。这种被 称为 "芯片之母" 的核心技术，贯穿芯片架构设计、物理验证、封装集成等所 有关键环节，堪称半导体产业的 "工业软件皇冠"。 一、 什么是 EDA？芯片设计的 "全流程总工程师" EDA 并非单一工具，而是一套覆盖芯片设计全生命周期的软件系统，如同 为工程师配备了 "超级大脑"。从千亿晶体管的布局规划到纳米级的信号完整 性验证，没有 EDA 的支撑，现代芯片设计将寸步难行。 其核心价值体现在三大环节：前端设计中，EDA 工具完成芯片架构搭建与 逻辑仿真，确保功能符合需求；后端实现阶段，通过物理设计工具完成晶体管布 局、布线与时序优化，在性能、功耗与面积间找到最优平衡；封装测试环节，则 借助专用工具解决多芯片集成的热仿真、信号干扰等问题。以 7nm 制程芯片 为例，其设计需处理超 1000 亿个晶体管的连接关系，传统人工方式需数百年， 而 EDA 工具可将周期压缩至 6 ...

Financial Data and Key Metrics Changes - In Q1 2026, the company achieved total revenue of $2.41 billion, at the high end of guidance, with non-GAAP EPS of $3.77, exceeding expectations [15][16] - Non-GAAP operating margin was reported at 42.1%, reflecting strong execution and financial discipline [15][16] - The backlog at the end of the quarter was $11.3 billion, indicating a resilient business model [15] Business Line Data and Key Metrics Changes - The Design Automation segment generated approximately $2 billion in revenue, driven by strong growth in hardware-assisted verification and Ansys contributions [17] - The Design IP segment revenue was $407 million, down approximately 6% year-over-year, with expectations for a transitional year [17] - Ansys revenue was approximately $886 million, reflecting robust demand for system-level digital engineering and AI-enabled design flows [16][17] Market Data and Key Metrics Changes - China revenue grew approximately 21% year-over-year, primarily due to Ansys inclusion, although excluding Ansys, revenue declined slightly [16] - The company noted subdued design starts in consumer, automotive, and industrial markets, despite a robust AI infrastructure build-out [6][8] Company Strategy and Development Direction - The company aims to drive sustainable growth and margin expansion by advancing technology leadership and focusing on integrated silicon-to-system engineering solutions [14] - The integration of Ansys is progressing well, with expectations to deliver joint solutions in FY 2027 [67] - The company is prioritizing investments in high-growth segments of the silicon market while divesting from non-core areas like the ARC processor business [56] Management's Comments on Operating Environment and Future Outlook - Management expressed confidence in the IP business driven by robust design starts, particularly in the AI segment [25] - The geopolitical and macroeconomic uncertainties, particularly in China, are impacting customer commitments and demand [70] - The company anticipates continued strong performance across all segments, with a focus on delivering joint solutions that leverage both Synopsys and Ansys capabilities [67][70] Other Important Information - The company has replenished its stock repurchase program with authorization to buy up to $2 billion of common stock [19] - Free cash flow for Q1 was approximately $822 million, with total cash and short-term investments of $2.2 billion [18] Q&A Session Summary Question: Insights on the IP segment and expected growth - Management highlighted confidence in the IP business due to robust design starts and evolving standards, with expectations for a pickup in the second half of the year [25][26] Question: Seasonality of bookings and renewal activity - Management noted that backlog is strong at $11.3 billion, with renewal timing affecting bookings but overall confidence in customer demand [35] Question: Ansys business forecastability - Management indicated that Ansys has broad market opportunities and is expected to grow, with the integration into Synopsys enhancing forecastability [46][67] Question: Impact of the NVIDIA partnership - The partnership is seen as a deep commitment to accelerate product development, particularly in GPU acceleration and digital twin opportunities [91][93] Question: Customer engagement with AgentEngineer - Management reported progress in customer engagement with AgentEngineer, focusing on both front-end and back-end applications [99] Question: Clarification on GAAP EPS guidance - The difference in GAAP and non-GAAP EPS is primarily due to amortization schedules and restructuring costs [101]

Financial Data and Key Metrics Changes - The company achieved total revenue of $2.41 billion in Q1 2026, at the high end of guidance, primarily due to the timing of Ansys deals [15][16] - Non-GAAP EPS was reported at $3.77, exceeding expectations, while GAAP EPS was $0.34 [15][17] - The non-GAAP operating margin was 42.1%, reflecting strong execution and financial discipline [15][16] - Backlog ended at $11.3 billion, indicating a resilient business model [15][16] Business Line Data and Key Metrics Changes - Design Automation segment revenue was approximately $2 billion, with strong growth in hardware-assisted verification [17] - Design IP segment revenue was $407 million, down approximately 6% year-over-year, indicating a transitional year for the business [17][19] - Ansys revenue was approximately $886 million, driven by robust demand for system-level digital engineering and multiphysics simulation [15][16] Market Data and Key Metrics Changes - China revenue grew approximately 21% year-over-year due to the inclusion of Ansys, although excluding Ansys, revenue declined slightly [16] - The company noted subdued design starts in consumer, automotive, and industrial markets, despite signals of modest recovery [7][8] Company Strategy and Development Direction - The company is focused on delivering on the technology promise of Synopsys plus Ansys, with a strong emphasis on AI-driven design capabilities [5][14] - The integration of Ansys is progressing well, with expectations for joint solutions to be monetized starting in FY 2027 [67] - The company aims to drive sustainable growth and margin expansion by advancing technology leadership and focusing on high-demand segments [13][14] Management's Comments on Operating Environment and Future Outlook - Management highlighted the ongoing geopolitical and macroeconomic uncertainties, particularly regarding China [8] - The company remains confident in its IP business due to robust design starts and evolving standards [25][26] - Management expects double-digit growth in EDA and mid-teens growth in IP, with a focus on capturing market opportunities [108] Other Important Information - The company has replenished its stock repurchase program with authorization to purchase up to $2 billion of common stock [19] - Free cash flow was approximately $822 million in Q1, with cash and short-term investments totaling $2.2 billion [18] Q&A Session Summary Question: Insights on the IP segment and expected growth - Management expressed confidence in the IP business driven by robust design starts and evolving standards, with expectations for a pickup in the second half of the year [25][26] Question: Seasonality of bookings and renewal activity - Management noted that backlog is strong at $11.3 billion, and renewal timing can cause fluctuations, but overall confidence remains high [35] Question: Ansys business forecastability - Management indicated that Ansys has broad market opportunities and is expected to perform well across various segments, despite accounting variability [46][49] Question: Rationale behind divesting the ARC processor business - The company is focusing on enhancing its interface IP business, believing it presents a larger growth opportunity compared to the ARC business [56] Question: Cost and revenue synergies from the Ansys acquisition - Management is on track to achieve $400 million in revenue and cost synergies by year four, with efforts to accelerate these synergies in the first two years [67] Question: Performance in China and competitive landscape - Management acknowledged challenges in China due to restrictions but noted that the Ansys portfolio performed well, while Synopsys's IP business faced some headwinds [70] Question: Concerns about IP delivery and customer design starts - Management reassured that they are aligned with customer schedules and are prioritizing resources to meet delivery timelines for critical IP titles [75][76]

Financial Data and Key Metrics Changes - The company reported total revenue of $2.41 billion for Q1 2026, at the high end of guidance, primarily due to timing of Ansys deals [15] - Non-GAAP operating margin was 42.1%, and non-GAAP EPS was $3.77, exceeding expectations [13][16] - Backlog ended at $11.3 billion, indicating a strong and resilient business model [13] Business Line Data and Key Metrics Changes - Design Automation segment revenue was approximately $2 billion, with strong growth in hardware-assisted verification [16] - Design IP segment revenue was $407 million, down approximately 6% year-over-year, indicating a transitional year for the business [16] - Ansys revenue was approximately $886 million, reflecting strong demand for system-level digital engineering and multiphysics simulation [15][16] Market Data and Key Metrics Changes - China revenue grew approximately 21% year-over-year due to the inclusion of Ansys, although excluding Ansys, revenue declined slightly [15] - The company noted a robust design start activity for AI compute, while design starts in consumer, automotive, and industrial markets remained subdued [4][5] Company Strategy and Development Direction - The company is focused on delivering technology promises from the integration of Synopsys and Ansys, with a strong emphasis on AI-driven design capabilities [4][12] - The strategy includes advancing technology leadership and focusing on sustainable growth and margin expansion [11][12] - The planned sale of the processor IP solutions business to GlobalFoundries is aimed at sharpening focus on interconnect and foundation IP [10] Management's Comments on Operating Environment and Future Outlook - Management expressed confidence in the IP business driven by robust design starts, particularly in the AI segment [24] - The company anticipates continued demand for silicon-to-system solutions, particularly in industries like semiconductors, aerospace, and automotive [6][10] - Management acknowledged challenges in the Chinese market due to geopolitical factors but remains optimistic about the overall demand for their products [68] Other Important Information - The company has replenished its stock repurchase program with authorization to purchase up to $2 billion of common stock [18] - Free cash flow was approximately $822 million in Q1, with total debt at $10 billion [17] Q&A Session Summary Question: Insights on the IP segment and expected growth - Management highlighted confidence in the IP business due to robust design starts and evolving standards, with expectations for a pickup in the second half of the year [24][25] Question: Seasonal trends in bookings and renewal activity - Management noted that backlog is strong at $11.3 billion, and renewal timing can cause fluctuations, but overall confidence remains high [34] Question: AI's impact on the business - Management stated that AI is amplifying their strategic advantage rather than disrupting it, with ongoing developments in AI-driven design capabilities [5][42] Question: Ansys business forecastability - Management expressed confidence in Ansys's ability to service multiple market segments, indicating broad growth opportunities despite accounting variability [44][46] Question: Updates on the NVIDIA partnership - The partnership is focused on GPU acceleration and creating digital twins for physical AI opportunities, with expectations for product delivery in 2026 [90][92]

Core Insights - Synopsys, Inc. is enhancing its role in semiconductor design through an expanded collaboration with Taiwan Semiconductor Manufacturing Company (TSMC) to meet the increasing demand for high-performance AI and system-on-chip (SoC) technologies [1][5] Collaboration with TSMC - Synopsys has certified its digital and analog design flows on TSMC's N2P and A16 processes, utilizing the NanoFlex architecture to optimize chip performance, reduce power consumption, and accelerate time-to-market [2][10] - The IC Validator certification for TSMC A16 improves physical verification, facilitating faster and more reliable design sign-offs [2] - The 3DIC Compiler platform supports advanced 3D stacking and CoWoS packaging technologies, contributing to multiple customer tape-outs and enhancing productivity for complex multi-die designs [3][10] - Synopsys is also collaborating with TSMC on silicon photonics, utilizing AI-optimized photonic flow to address performance and thermal challenges in AI systems [3] Comprehensive IP Portfolio - Synopsys' extensive IP portfolio supports leading standards such as PCIe 7.0, UCIe, HBM4, and 1.6T Ethernet, with dedicated automotive IP for TSMC's N5A and N3A nodes targeting key markets like AI, automotive, and high-performance computing [4] Strategic Partnerships - In addition to TSMC, Synopsys has formed strong partnerships with Intel Corporation and Arm Holdings to advance chip design and innovation [6][9] - The collaboration with Intel focuses on enabling design flows and IP solutions for Intel's latest 18A process node, optimizing performance, power, and area for next-generation processors [7] - Synopsys provides EDA tools and a broad IP portfolio compatible with Arm's CPU, GPU, and AI cores, ensuring quick integration of components and meeting power and performance targets [8][9] Industry Positioning - The strengthened collaboration with TSMC reinforces Synopsys' position as a critical partner in advanced chip development, well-positioned to drive long-term growth in the AI and multi-die era [5]

Core Insights - Synopsys, Inc. is collaborating closely with TSMC to deliver advanced EDA and IP products that support TSMC's leading-edge processes and packaging technologies, particularly in AI chip and multi-die design [2][3] - The partnership has resulted in multiple customer tape-outs, showcasing the effectiveness of the 3DIC Compiler platform and the comprehensive IP portfolio optimized for TSMC's advanced technologies [2][3] Collaboration and Innovation - Synopsys has made certified digital and analog flows available on TSMC's N2P and A16 processes, utilizing TSMC NanoFlex architecture to optimize performance and power [3][4] - The collaboration includes robust automotive IP solutions for TSMC N5A and N3A processes, ensuring high safety, security, and reliability while maximizing performance [3][4] Technology Advancements - The 3DIC Compiler platform supports advanced 3D stacking and CoWoS packaging technologies, enabling multiple customer tape-outs and enhancing productivity [6][7] - An AI-optimized photonic flow for TSMC-COUPE technology has been developed to improve system performance and address multi-wavelength and thermal requirements [7][8] IP Portfolio and Market Impact - Synopsys offers the industry's broadest IP portfolio optimized for low power on TSMC N2/N2P processes, which accelerates the path to silicon success and reduces integration risk [4][8] - The IP portfolio supports high-performance standards, including HBM4, 1.6T Ethernet, UCIe, PCIe 7.0, and UALink, catering to automotive, IoT, and HPC applications [8] Verification and Design Flow - Synopsys IC Validator signoff physical verification solution is certified for TSMC A16 process, enhancing DRC and LVS checking capabilities [5] - Ongoing collaboration on design flow development for TSMC's A14 process is expected to yield its first process design kit release in late 2025 [3][5]

Global EDA Industry Performance - The global EDA industry is projected to grow by 11% year-on-year in Q4 2024, reaching $4.9 billion, despite a weak performance in the Chinese market [3][4] - The EDA software industry is characterized by high technical barriers, talent reserves, user collaboration, and significant capital scale, with a market concentration exceeding 70% among the top three companies: Cadence, Synopsys, and Siemens EDA [5] Growth Drivers in EDA - The increasing demand for edge computing and high-performance computing (HPC) chips is driving the need for more complex and automated EDA solutions [6] - The rise of cloud solutions facilitates seamless collaboration and enhances accessibility for global design teams [6] - The integration of AI and machine learning algorithms into workflows is optimizing design accuracy and efficiency, reducing costly errors, and accelerating time-to-market [6] Segment Performance - CAE (Computer-Aided Engineering) revenue grew by 10.9% to $1.6969 billion [7] - IC physical design and verification saw a 15.4% increase, reaching $797.9 million [7] - PCB & MCM (Printed Circuit Board & Multi-Chip Module) revenue increased by 15.9% to $476.2 million [7] - Semiconductor IP (SIP) revenue grew by 7.9% to $1.7607 billion, with some companies reporting declines [7] - Service revenue increased by 11% to $195.6 million, reflecting strong design demand amid talent shortages [7] - IC packaging design revenue surged by 70%, indicating a significant rise in advanced packaging demand [7] AI's Role in EDA - EDA vendors are leveraging AI to optimize software engines, processes, and workflows, which is crucial for scalable and reliable outcomes [8] - AI applications in EDA include automating repetitive tasks, enhancing design optimization, and providing intelligent assistance through generative AI [11][12] - AI-driven tools can significantly reduce design cycles and improve accuracy, as demonstrated by Synopsys' AI-driven EDA tools [11] Future Outlook - The emergence of Chiplet technology is transforming chip design and manufacturing paradigms, necessitating new tool support for architecture exploration and signal integrity analysis [13] - EDA tools must evolve to support heterogeneous integration design, with companies like Synopsys and Cadence developing specialized tool suites for Chiplet design [13][15] - The collaboration between EDA tools and IP design capabilities will be critical for future competitiveness, as traditional IP markets face saturation [14]

Core Insights - Synopsys and Intel Foundry have announced collaborations to enhance EDA and IP solutions for advanced semiconductor processes, specifically targeting the Intel 18A and 18A-P process nodes [2][5][6] EDA and IP Solutions - Synopsys has introduced certified AI-driven digital and analog design flows for the Intel 18A process node and production-ready EDA flows for the Intel 18A-P process node, which includes advanced technologies like RibbonFET and PowerVia [2][6] - The collaboration aims to accelerate the development of AI and high-performance computing (HPC) chip designs, providing comprehensive technologies for mutual customers [5][6] Multi-Die Design Innovation - Synopsys and Intel Foundry are working together to enable the new Embedded Multi-die Interconnect Bridge-T (EMIB-T) technology, which combines benefits from both 2.5D and 3D packaging technologies [3][9] - The EMIB-T reference flow is powered by Synopsys' unified exploration-to-signoff platform, facilitating efficient designs and high-quality results [9] Power, Performance, and Area (PPA) Optimization - Synopsys' EDA flows are optimized for power and area, leveraging Intel's PowerVia technology for enhanced thermal-aware implementations [6][10] - The collaboration has resulted in significant advancements in power, performance, and area (PPA) for designs on Intel 18A and Intel 18A-P process nodes [6][10] Ecosystem Expansion - Synopsys has joined the Intel Foundry Accelerator Design Services Alliance and the Intel Foundry Accelerator Chiplet Alliance to further support the semiconductor ecosystem [11] - This membership aims to enhance interoperability and manufacturability for multi-die chip designs on Intel 18A [11]

Core Insights - Synopsys, in collaboration with TSMC, is enhancing EDA and IP solutions for advanced semiconductor designs, particularly focusing on AI chip design and 3D multi-die innovations [2][3] - The partnership aims to accelerate the adoption of Angstrom-scale designs through certified EDA flows on TSMC's latest processes, including A16 and N2P [2][4] Collaboration and Innovation - Synopsys and TSMC are working together to provide certified digital and analog flows that improve design productivity and optimization for advanced semiconductor processes [2][3] - The collaboration includes the development of EDA flows for TSMC's A14 process, demonstrating Synopsys' commitment to high-performance design solutions [5] Technology Advancements - Synopsys' 3DIC Compiler supports TSMC's CoWoS technology, enabling unprecedented 5.5x reticle interposer sizes, which is crucial for next-generation HPC and AI chips [7] - The integration of multi-physics analysis and signoff solutions with Ansys simulation technologies enhances power, thermal, and signal integrity analysis for advanced designs [7] IP Solutions and Market Impact - Synopsys offers a broad portfolio of silicon-proven IP solutions for TSMC's advanced processes, which are essential for achieving low power and high performance in various applications, including HPC and automotive [8][9] - The successful deployment of Synopsys IP in thousands of designs helps reduce integration risk while meeting stringent power, performance, and area targets [8] Industry Engagement - Synopsys is actively participating in industry events, such as the TSMC Tech Symposium, to showcase its innovations and strengthen partnerships within the semiconductor ecosystem [10]