Core Viewpoint - TSMC's CoPoS packaging technology mass production timeline is delayed from 2027 to 2029-2030 due to technical challenges, which may influence NVIDIA's plans for its Rubin Ultra GPU and shift focus to multi-chip module architecture [1] Group 1: TSMC's CoPoS Technology - TSMC's CoPoS (chip-on-panel-on-substrate) technology aims to enhance area utilization through larger panel sizes (e.g., 310x310mm) to meet AI GPU demands from clients like NVIDIA [1] - The delay in CoPoS mass production is attributed to immaturity in technology, particularly in managing panel and wafer discrepancies, larger area warpage control, and additional redistribution layers (RDL) [1] Group 2: Impact on AI Industry - Nomura's analysis suggests that TSMC may redirect its 2026 chip backend capital expenditures towards other technologies such as WMCM and SoIC, with CoWoS capacity allocation becoming a critical monitoring point [1] - The postponement of CoPoS could lead NVIDIA to adopt a multi-chip module architecture similar to Amazon's Trainium 2 design for its 2027 product launch [1]

Core Viewpoint - Nomura indicates that TSMC's CoPoS packaging technology mass production timeline may be delayed from the original plan of 2027 to 2029-2030, potentially forcing NVIDIA to shift its chip design strategy for the Rubin Ultra GPU to an MCM architecture to avoid limitations of single-module packaging [2][3][4]. Group 1: TSMC's CoPoS Technology Delay - TSMC's CoPoS (chip-on-panel-on-substrate) technology aims to enhance area utilization through larger panel sizes (e.g., 310x310mm) to meet AI GPU demands [4]. - The delay in CoPoS mass production is attributed to technical challenges, particularly in managing panel and wafer discrepancies, warpage control, and additional redistribution layers (RDL) [4][5]. - The expected mass production timeline has shifted from 2027 to potentially late 2029 [4][5]. Group 2: Impact on NVIDIA's Product Strategy - The delay in CoPoS may compel NVIDIA to adopt an MCM architecture for the Rubin Ultra GPU, distributing four Rubin GPUs across two modules connected via a substrate [5][6]. - This adjustment is similar to Amazon's AWS Trainium 2 design, which utilizes CoWoS-R and MCM to integrate computing chips and HBM on a single substrate [6]. - While this change may help NVIDIA mitigate delays, it could also increase design complexity and costs [6]. Group 3: TSMC's Capital Expenditure Adjustments - TSMC's capital expenditure allocation may shift towards wafer-level multi-chip modules (WMCM) and system-on-chip (SoIC) technologies due to the CoPoS delay [7]. - Nomura maintains its forecast for TSMC's CoWoS capacity, expecting monthly wafer production to reach 70,000 and 90,000-100,000 by the end of 2025 and 2026, respectively [7]. - The report warns that market expectations for WMCM may be overly optimistic, while those for SoIC are more conservative [8].

Group 1 - TSMC plans to invest $100 billion in advanced semiconductor manufacturing in the U.S. by March 2025, including three new fabs, two advanced packaging facilities, and a major R&D center [1] - TSMC is accelerating the construction of its third fab at Fab 21 in Phoenix, Arizona, with plans to build two dedicated buildings nearby for advanced packaging services [1] - The first advanced packaging facility, AP1, is set to begin construction in 2028, while the second facility, AP2, has no specific start date yet [2] Group 2 - The two advanced packaging facilities will focus on CoPoS and SoIC packaging technologies, with CoPoS utilizing a 310×310 mm rectangular panel to improve area utilization and capacity [2] - SoIC technology involves stacking memory chips beneath the processing core, validated in AMD's Ryzen X3D processor, with testing production for CoPoS planned to start in 2026 [2] - AP1 is expected to be operational by the end of 2029 or early 2030, aligning with TSMC's delivery timelines [2]