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NVM IP,至关重要
半导体行业观察· 2026-02-28 01:14
公众号记得加星标⭐️,第一时间看推送不会错过。 随着 SoC 设计向先进节点发展,以及人工智能、新型传感器技术和严格的质量标准带来的新需求, 非易失性存储器的选择变得越来越复杂。 2025 年第二份年度 NVM 调查报告于 12 月完成,该报告反映出,市场仍然依赖于现有技术,但为 了应对这些新的设计和生产限制,市场正在越来越多地尝试替代方案。 超过80%的受访者表示他们正在使用或评估嵌入式非易失性存储器(NVM)技术。20%的受访者目 前正在寻找NVM,近30%的受访者预计将在未来一年内选择NVM IP。总而言之,这表明该市场既成 熟又活跃。相当一部分近期决策尚未做出,这意味着各种竞争技术之间仍存在很大的发展空间。 当被问及嵌入式非易失性存储器(NVM)选择标准的重要性时,结果强调了实用性。可靠性、耐久 性和数据保持能力均名列前茅,加权平均分均远高于3.0(满分4.0),证实它们仍然是嵌入式NVM 选择的基础要求。工艺可扩展性紧随其后,得分也超过3.0,反映出将传统嵌入式NVM扩展到嵌入式 闪存无法扩展的先进几何结构中变得越来越困难。电源效率的得分也超过3.0。集成风险和长期可预 测性仅略逊一筹,表明制造准备 ...
MCU巨头,全部明牌
半导体行业观察· 2026-01-01 01:26
Core Viewpoint - The embedded computing world is undergoing a transformation where AI is reshaping the architecture of MCUs, moving from traditional designs to those that natively support AI workloads while maintaining reliability and low power consumption [2][5]. Group 1: MCU Evolution - The integration of NPU in MCUs is driven by the need for real-time control and stability in embedded systems, particularly in industrial and automotive applications [3][4]. - NPU allows for "compute isolation," enabling AI inference to run independently from the main control tasks, thus preserving real-time performance [3][5]. - Current edge AI applications typically utilize lightweight neural network models, making hundreds of GOPS sufficient for processing, which contrasts with the high TOPS requirements in mobile and server environments [5]. Group 2: Major MCU Players' Strategies - TI focuses on deep integration of NPU capabilities in real-time control applications, enhancing safety and reliability in industrial and automotive scenarios [7][8]. - Infineon leverages the Arm ecosystem to create a low-power AI MCU platform, aiming to reduce development barriers for edge AI applications across various sectors [9][10]. - NXP emphasizes hardware scalability and a full-stack software approach with its eIQ Neutron NPU, targeting diverse neural network models while ensuring low power and real-time response [11][12]. - ST aims for high-performance edge visual applications with its self-developed NPU, pushing the boundaries of traditional MCU AI capabilities [13][14]. - Renesas combines high-performance cores with dedicated NPU and security features, focusing on reliable edge AIoT applications [15][16]. Group 3: New Storage Technologies - The introduction of NPU in MCUs necessitates a shift from traditional Flash storage to new storage technologies that can handle the demands of AI workloads and frequent updates [17][18]. - New storage solutions like MRAM, RRAM, PCM, and FRAM are emerging to address the limitations of Flash, offering advantages in reliability, speed, and endurance [21][22][25][28][30]. - MRAM is particularly suited for automotive and industrial applications due to its high reliability and endurance, with companies like NXP and Renesas leading in its adoption [22][23][24]. - RRAM offers benefits in speed and flexibility, making it a strong candidate for AI applications, with Infineon actively promoting its integration into next-generation MCUs [25][26][27]. - PCM provides high storage density and efficiency, suitable for complex embedded systems, with ST advocating for its use in advanced MCU designs [28][29]. Group 4: Future Implications - The dominance of Flash storage is being challenged as new storage technologies demonstrate superior performance and reliability for embedded systems [33]. - The integration of NPU and new storage technologies in MCUs represents a shift towards system-level optimization, enhancing overall performance and efficiency [33]. - The transformation in the MCU market presents structural opportunities for domestic manufacturers to innovate and compete against established international players [33].
后eFlash时代:MCU产业格局重塑
半导体芯闻· 2025-05-14 10:10
Core Viewpoint - The semiconductor industry is shifting from a singular focus on process miniaturization to diversified innovation, with advanced packaging technologies and specialty processes driving performance optimization and differentiation in the market [1][2]. Group 1: Market Trends and Growth - The global specialty process market has surpassed $50 billion, with a compound annual growth rate (CAGR) of 15%, significantly outpacing the average growth rate of the semiconductor industry [1]. - Companies like TSMC, UMC, and SMIC are accelerating their investments in specialty processes, with TSMC establishing itself as a global benchmark through its extensive technology portfolio [2][4]. Group 2: TSMC's Specialty Process Landscape - TSMC offers a comprehensive range of specialty processes, including automotive, ultra-low power (ULP)/IoT, RF, embedded non-volatile memory (eNVM), high-voltage display, and CMOS image sensors (CIS) [4]. - TSMC's automotive-grade processes are designed for high reliability and long lifecycle, supporting advanced driver-assistance systems (ADAS) and smart cockpit applications [4]. - The N4e process is optimized for ultra-low power IoT AI devices, balancing performance and cost effectively [4]. Group 3: Innovations in Non-Volatile Memory (NVM) - TSMC is addressing the limitations of traditional eFlash technology by advancing embedded NVM technologies such as RRAM and MRAM, which are expected to replace eFlash in automotive and IoT applications [6][7]. - RRAM technology is being commercialized, with TSMC's 22nm RRAM already certified for automotive applications, and 12nm RRAM expected to follow suit [6][7]. - MRAM technology is also being developed for automotive applications, with NXP and TSMC collaborating on 16nm embedded MRAM for high-end automotive MCUs [20][21]. Group 4: Competitive Landscape and Future Directions - Major MCU manufacturers are exploring various new storage technologies, including eRRAM, eMRAM, ePCM, and eFeRAM, to enhance performance and reduce power consumption [16][31]. - The market for embedded NVM is projected to grow significantly, with wafer production expected to increase from approximately 3 KWPM in 2023 to about 110 KWPM by 2029, indicating a CAGR of around 80% [29]. - TSMC plans to integrate advanced processes with specialty technologies to support the evolution of chip architecture from "functional integration" to "system reconstruction" [8][34].