PRIMER 23 March 2026 China Semiconductors on 23-Mar-2026 Future of Tech: AI Datacenter Networking Primer Qingyuan Lin, Ph.D. +852 2123 2654 qingyuan.lin@bernsteinsg.com Stacy A. Rasgon, Ph.D. +1 213 559 5917 stacy.rasgon@bernsteinsg.com Francis Ma +852 2123 2626 francis.ma@bernsteinsg.com +852 2123 2694 zheng.cui@bernsteinsg.com Arpad von Nemes +1 917 344 8461 arpad.vonnemes@bernsteinsg.com Alrick Shaw +1 917 344 8454 alrick.shaw@bernsteinsg.com See the Disclosure Appendix of this report for required disclo ...

Financial Data and Key Metrics Changes - In Q1 2026, the company achieved total revenue of $2.41 billion, at the high end of guidance, with non-GAAP EPS of $3.77, exceeding expectations [15][16] - Non-GAAP operating margin was reported at 42.1%, reflecting strong execution and financial discipline [15][16] - The backlog at the end of the quarter was $11.3 billion, indicating a resilient business model [15] Business Line Data and Key Metrics Changes - The Design Automation segment generated approximately $2 billion in revenue, driven by strong growth in hardware-assisted verification and Ansys contributions [17] - The Design IP segment revenue was $407 million, down approximately 6% year-over-year, with expectations for a transitional year [17] - Ansys revenue was approximately $886 million, reflecting robust demand for system-level digital engineering and AI-enabled design flows [16][17] Market Data and Key Metrics Changes - China revenue grew approximately 21% year-over-year, primarily due to Ansys inclusion, although excluding Ansys, revenue declined slightly [16] - The company noted subdued design starts in consumer, automotive, and industrial markets, despite a robust AI infrastructure build-out [6][8] Company Strategy and Development Direction - The company aims to drive sustainable growth and margin expansion by advancing technology leadership and focusing on integrated silicon-to-system engineering solutions [14] - The integration of Ansys is progressing well, with expectations to deliver joint solutions in FY 2027 [67] - The company is prioritizing investments in high-growth segments of the silicon market while divesting from non-core areas like the ARC processor business [56] Management's Comments on Operating Environment and Future Outlook - Management expressed confidence in the IP business driven by robust design starts, particularly in the AI segment [25] - The geopolitical and macroeconomic uncertainties, particularly in China, are impacting customer commitments and demand [70] - The company anticipates continued strong performance across all segments, with a focus on delivering joint solutions that leverage both Synopsys and Ansys capabilities [67][70] Other Important Information - The company has replenished its stock repurchase program with authorization to buy up to $2 billion of common stock [19] - Free cash flow for Q1 was approximately $822 million, with total cash and short-term investments of $2.2 billion [18] Q&A Session Summary Question: Insights on the IP segment and expected growth - Management highlighted confidence in the IP business due to robust design starts and evolving standards, with expectations for a pickup in the second half of the year [25][26] Question: Seasonality of bookings and renewal activity - Management noted that backlog is strong at $11.3 billion, with renewal timing affecting bookings but overall confidence in customer demand [35] Question: Ansys business forecastability - Management indicated that Ansys has broad market opportunities and is expected to grow, with the integration into Synopsys enhancing forecastability [46][67] Question: Impact of the NVIDIA partnership - The partnership is seen as a deep commitment to accelerate product development, particularly in GPU acceleration and digital twin opportunities [91][93] Question: Customer engagement with AgentEngineer - Management reported progress in customer engagement with AgentEngineer, focusing on both front-end and back-end applications [99] Question: Clarification on GAAP EPS guidance - The difference in GAAP and non-GAAP EPS is primarily due to amortization schedules and restructuring costs [101]

Financial Data and Key Metrics Changes - The company reported total revenue of $2.41 billion for Q1 2026, at the high end of guidance, primarily due to timing of Ansys deals [15] - Non-GAAP operating margin was 42.1%, and non-GAAP EPS was $3.77, exceeding expectations [13][16] - Backlog ended at $11.3 billion, indicating a strong and resilient business model [13] Business Line Data and Key Metrics Changes - Design Automation segment revenue was approximately $2 billion, with strong growth in hardware-assisted verification [16] - Design IP segment revenue was $407 million, down approximately 6% year-over-year, indicating a transitional year for the business [16] - Ansys revenue was approximately $886 million, reflecting strong demand for system-level digital engineering and multiphysics simulation [15][16] Market Data and Key Metrics Changes - China revenue grew approximately 21% year-over-year due to the inclusion of Ansys, although excluding Ansys, revenue declined slightly [15] - The company noted a robust design start activity for AI compute, while design starts in consumer, automotive, and industrial markets remained subdued [4][5] Company Strategy and Development Direction - The company is focused on delivering technology promises from the integration of Synopsys and Ansys, with a strong emphasis on AI-driven design capabilities [4][12] - The strategy includes advancing technology leadership and focusing on sustainable growth and margin expansion [11][12] - The planned sale of the processor IP solutions business to GlobalFoundries is aimed at sharpening focus on interconnect and foundation IP [10] Management's Comments on Operating Environment and Future Outlook - Management expressed confidence in the IP business driven by robust design starts, particularly in the AI segment [24] - The company anticipates continued demand for silicon-to-system solutions, particularly in industries like semiconductors, aerospace, and automotive [6][10] - Management acknowledged challenges in the Chinese market due to geopolitical factors but remains optimistic about the overall demand for their products [68] Other Important Information - The company has replenished its stock repurchase program with authorization to purchase up to $2 billion of common stock [18] - Free cash flow was approximately $822 million in Q1, with total debt at $10 billion [17] Q&A Session Summary Question: Insights on the IP segment and expected growth - Management highlighted confidence in the IP business due to robust design starts and evolving standards, with expectations for a pickup in the second half of the year [24][25] Question: Seasonal trends in bookings and renewal activity - Management noted that backlog is strong at $11.3 billion, and renewal timing can cause fluctuations, but overall confidence remains high [34] Question: AI's impact on the business - Management stated that AI is amplifying their strategic advantage rather than disrupting it, with ongoing developments in AI-driven design capabilities [5][42] Question: Ansys business forecastability - Management expressed confidence in Ansys's ability to service multiple market segments, indicating broad growth opportunities despite accounting variability [44][46] Question: Updates on the NVIDIA partnership - The partnership is focused on GPU acceleration and creating digital twins for physical AI opportunities, with expectations for product delivery in 2026 [90][92]

Core Insights - PCIe is the bus standard in servers, with continuous improvements in data transfer rates, expected to reach 256GT/s with the upcoming PCIe 8.0 specification by 2028 [1] - The number of PCIe lanes in server CPUs is increasing, which will drive demand for PCIe slots [2] - The transition to PCIe 6.0 in future server CPUs will create additional demand for PCIe Retimer chips to maintain signal integrity over longer distances [3] Group 1: PCIe Technology Development - PCIe is a high-speed serial computer expansion bus standard used for data exchange between CPUs and other devices, addressing bandwidth limitations of the older PCI standard [1] - The PCIe standard has evolved, with PCIe 5.0 achieving a data transfer rate of 32GT/s and a single lane bandwidth of approximately 4GB/s, allowing for a throughput of 128GB/s in x16 configuration [1] - The PCI-SIG association is developing PCIe 8.0, which is expected to enhance data rates significantly by 2025 [1] Group 2: Server CPU and PCIe Lane Configuration - The configuration of PCIe lanes is crucial for device performance, with common configurations being x1, x4, x8, and x16 [2] - Intel's sixth-generation server CPUs can support up to 88 PCIe 5.0 lanes, a 10% increase from the previous generation, while performance cores can support up to 96 lanes, a 20% increase [2] - As the number of PCIe lanes increases, the demand for PCIe slots is expected to rise correspondingly [2] Group 3: Future Trends and Opportunities - Intel's sixth-generation server CPUs support PCIe 5.0, while AMD's upcoming EPYC "Venice" processors are expected to support PCIe 6.0, anticipated for release in 2026 [3] - The insertion loss budget for PCIe 6.0 is set at 32dB, necessitating the use of PCI Retimer chips to enhance signal quality and extend transmission distances [3] - PCI Retimer chips are essential for addressing issues related to signal integrity and loss in high-speed data transmission environments [3] Group 4: Investment Opportunities - Companies to watch include Hongteng Precision (06088), a PCIe slot supplier, and Lanke Technology (688008.SH, 06809), a supplier of PCIe Retimer chips [4] - Wan Tong Development (600246.SH) is noted for acquiring a PCIe Switch chip supplier, Shudu Technology, indicating strategic moves in the PCIe supply chain [4]

Core Viewpoint - Company focuses on the development of high-speed interface IP and high-performance analog IP, indicating a strategic emphasis on advanced technology solutions in the semiconductor industry [1] Group 1: High-Speed Interface IP - The company is currently developing various high-speed interface IPs, including DDR, SerDes, PCIe, MIPI, PSRAM, and TCAM [1] Group 2: High-Performance Analog IP - The company is also engaged in the research and development of high-performance analog IPs, which include ADC, PLL, and PMU [1]

Core Insights - Credo Technology Group Holding Ltd (CRDO) is experiencing rapid expansion driven by the AI infrastructure cycle, resulting in a 272% year-over-year revenue increase to $268 million in Q2 of fiscal 2026 [1][9] - The company has a strong cash position of $813.6 million, allowing it to invest in growth opportunities and maintain a solid balance sheet [1][4] - Management is focused on multi-billion-dollar growth initiatives, including Zero-Flap optics and active LED cables, with a total market opportunity expected to exceed $10 billion [3] Financial Performance - Cash flow from operating activities reached $61.7 million, an increase of $7.5 million sequentially, while free cash flow was $38.5 million [2] - For fiscal Q3, Credo anticipates revenues between $335 million and $345 million, indicating a 27% sequential growth at the midpoint, and expects over 170% year-over-year growth for fiscal 2026 [5] Strategic Initiatives - The strong cash balance supports Credo's M&A efforts, enhancing access to new technologies and accelerating organic growth [4] - Recent acquisition of Hyperlume, a developer of microLED technology, exemplifies the company's strategy to broaden its market reach [4] Market Position and Valuation - CRDO shares have declined by 25.8% over the past month, compared to a 9.2% decline in the Electronics-Semiconductors industry [11] - The forward 12-month Price/Sales ratio for CRDO is 39.79, higher than the sector's average of 33.96 [12] - The Zacks Consensus Estimate for CRDO earnings for fiscal 2026 has been significantly revised upwards over the past 60 days, indicating positive market sentiment [13]

Core Viewpoint - The traditional computing architecture is insufficient for the efficient, low-energy, and large-scale collaborative AI training needs, leading to the trend of supernodes which significantly boosts the demand for Scale up-related hardware [1][3] Group 1: AI Hardware Capabilities - AI hardware capabilities are driven by three main factors: computing power (determined by GPU performance and quantity), storage capacity (high-bandwidth memory cache close to GPUs), and communication capacity (encompassing Scale up, Scale out, and Scale across scenarios) [1][2] Group 2: Market Trends and Projections - The market for Scale up switching chips is expected to reach nearly $18 billion by 2030, with a CAGR of approximately 28% from 2022 to 2030, driven by the demand for supernodes [3] - The construction of large-scale AI clusters necessitates extensive interconnectivity between nodes, leading to increased demand for Scale out hardware, while power resource limitations in single regions will promote the adoption of Scale across solutions [3] Group 3: Communication Protocols - Different communication protocols are required for Scale up and Scale out, with major companies developing proprietary protocols alongside third-party and smaller firms promoting public protocols [4] - Notable proprietary protocols for Scale up include NVIDIA's NVlink and AMD's Infinity Fabric, while public protocols include Broadcom's SUE and PCIe [4] Group 4: Domestic Hardware Development - The domestic production rate of communication hardware is currently very low, presenting a significant opportunity for domestic replacement in the market [5] - Companies like Shudao Technology and Shengke Communication are advancing towards commercialization of their products, indicating a growing domestic market potential [5] Group 5: Investment Opportunities - Beneficiaries of PCIe hardware include Wantong Development and Lanke Technology, while Ethernet hardware beneficiaries include Shengke Communication and ZTE [6]

Core Insights - Astera Labs is leading the development of semiconductor-based connectivity solutions for rack-scale AI infrastructure, emphasizing the shift towards unified computing platforms rather than individual servers [1][2] - The company is showcasing its ecosystem collaborations at the 2025 OCP Global Summit, highlighting the importance of open standards for AI Infrastructure 2.0 [1][2] Industry Trends - The AI infrastructure landscape is transitioning from server-level architectures to rack-scale systems, driven by significant investments from hyperscalers [2] - Open standards are essential for integrating diverse accelerators, interconnects, and management tools, enabling optimized solutions for specialized AI workloads [2] Ecosystem Collaborations - Astera Labs is collaborating with various industry leaders, including AMD, Arm, and Molex, to enhance AI infrastructure through high-performance connectivity solutions [3][4][9] - These partnerships focus on delivering reliable, high-speed cable solutions and ensuring robust signal integrity across rack-scale distances [3][9] Technical Innovations - The company is presenting technical sessions on UALink deployment strategies and PCIe 6 security considerations at the OCP Global Summit [2] - Astera Labs' Intelligent Connectivity Platform integrates multiple semiconductor-based technologies, including CXL, Ethernet, PCIe, and UALink, to create cohesive systems [13] Market Position - Astera Labs positions itself as a key player in the AI infrastructure market by providing purpose-built connectivity solutions grounded in open standards [13] - The company's collaborations aim to accelerate the adoption of open rack architectures, enhancing performance, interoperability, and scalability for customers [10][12]

Core Viewpoint - The release of the PCIe 8.0 standard marks a significant milestone in the evolution of PCIe technology, doubling the data transfer rate to 256GT/s and reinforcing its critical role in high-speed data transfer across various computing environments [1][38]. Group 1: Evolution of PCIe Technology - PCIe, introduced by Intel in 2001, has evolved from the original PCI standard, which had a maximum bandwidth of 133 MB/s, to a series of iterations that have consistently doubled the data transfer rates [3][14]. - The transition from PCI to PCIe represents a shift from parallel bus technology to a serial communication mechanism, significantly enhancing data transfer efficiency and reducing signal interference [9][11]. - The PCIe 1.0 standard initiated the serial interconnect revolution with a transfer rate of 2.5GT/s, while subsequent versions have seen substantial increases, culminating in the upcoming PCIe 8.0 [14][38]. Group 2: Key Features of PCIe - PCIe's architecture includes three core features: serial communication, point-to-point connections, and scalable bandwidth capabilities, which collectively enhance performance and reduce latency [9][11]. - The introduction of advanced signal processing techniques, such as CTLE in PCIe 3.0 and PAM4 modulation in PCIe 6.0, has been pivotal in maintaining signal integrity and supporting higher data rates [18][24]. - PCIe 8.0 is set to introduce new connector technologies and optimize latency and error correction mechanisms, ensuring reliability and efficiency in high-bandwidth applications [42][38]. Group 3: Market Applications and Trends - PCIe technology is predominantly utilized in cloud computing, accounting for over 50% of its market share, with increasing adoption in automotive and consumer electronics sectors [46][49]. - The demand for high-speed interconnects is driven by the growth of AI applications, high-performance computing, and data-intensive workloads, positioning PCIe as a foundational technology in these areas [45][51]. - Predictions indicate that the PCIe market in AI applications could reach $2.784 billion by 2030, with a compound annual growth rate of 22% [51]. Group 4: Competitive Landscape and Challenges - PCIe faces competition from proprietary interconnect technologies like NVLink and CXL, which offer higher bandwidth and lower latency for GPU communications [55][63]. - The establishment of the UALink alliance aims to create open standards for GPU networking, challenging the dominance of proprietary solutions and enhancing interoperability [56]. - Despite its established position, PCIe must navigate challenges related to bandwidth limitations and evolving market demands, necessitating continuous innovation and adaptation [64][71].

Core Insights - Credo Technology Group Holding Ltd. (CRDO) and Astera Labs, Inc (ALAB) are emerging players in high-speed connectivity solutions for AI and data center infrastructure, presenting an interesting comparison for investors [1] Group 1: CRDO Overview - CRDO's fiscal 2025 revenues increased by 126% year over year to $436.8 million, with fourth-quarter revenues surging 179.7% year over year to $170 million, indicating strong adoption of its connectivity solutions [2][9] - The company is gaining market presence in Ethernet and Active Electrical Cables (AECs), with AECs showing double-digit sequential growth in the fiscal fourth quarter [3] - CRDO's integrated approach, owning the entire stack of SerDes IP, Retimer ICs, and system-level design, enhances its innovation cycles and cost efficiency [3] - The optical business, particularly for Optical Digital Signal Processors (DSPs), is expected to drive the transition to 200 gig lane speeds, with CRDO's 3-nanometer 200-gig-per-lane optical DSP port speeds reaching up to 1.6 terabits per second [4] - Operating margin expanded by 2,500 basis points in fiscal 2025, showcasing the profitability of CRDO's business model [5] - For fiscal 2026, CRDO anticipates revenues to exceed $800 million, implying over 85% year-over-year growth [6] Group 2: ALAB Overview - Astera Labs reported a 144% year-over-year revenue growth in the last quarter, driven by its Aries and Taurus product lines [7][9] - The company is focusing on portfolio expansion with new products like Scorpio Fabric Switches and optical interconnects, which are expected to enhance its market position [10] - ALAB expects second-quarter 2025 revenues between $170 million and $175 million, reflecting a 7-10% quarter-over-quarter increase [11] - Increased R&D investment may impact margins if revenue growth does not keep pace, with operating expenses projected between $73 million and $75 million in the second quarter of 2025 [12] Group 3: Market Performance and Valuation - Over the past month, CRDO and ALAB have gained 13.2% and 41.8%, respectively [15] - CRDO is trading at a forward 12-month price/sales ratio of 19.30X, while ALAB's ratio is 24.64X [16] - Analysts have significantly revised estimates for CRDO's bottom line upward in the past 60 days, while ALAB has seen marginal upward revisions [20][21] Group 4: Investment Outlook - Both CRDO and ALAB are well-positioned to benefit from the growing AI-driven data center market [22] - CRDO currently holds a Zacks Rank 1 (Strong Buy), while ALAB has a Zacks Rank 3 (Hold), suggesting CRDO may be a better investment pick at this time [22]