CS 壁芯科技 | #进封装产业生态: | 合纵连横 | | 张晟彬 - 香港浪潮云 高级战略销售总监 | | --- | --- | | 14:20 | 异构集成技术赋能MEMS Stacking与3D IC创新发展 | | | 金文超 - 华润微电子 高级工程师 | | 14:40 | 基于典型应用沉淀的先进封装产业协同EDA解决方案 | | | 赵毅 - 硅芯科技 创始人&CEO | | 15:00 | 先进封装关键装备及核心技术突破 | | | 萧青晏 - 迈为技术 工艺应用开发院副院长 | | 15:20 | 大尺寸晶圆临时键合与精密减薄 | | | 万青 - 甬江实验室 异构集成研究中心主任 | | 15:40 · | 超大芯片之CoWoS与SOW | | | 陈勇辉 - 星空科技 总裁 | | 16:00 | 先进封装在大规模Al智章芯片领域当中的发展路径 | | | 谢建友 - 齐力半导体 董事长/总经理 | | 16:20 | 圆桌对话:先进封装驱动产业空前"合纵连横", | | | 从分工深化走向协同升级 | | 18:00 | 晩宴 | 参会指引 K 交通 与 入场 路线 >>> 地铁出 ...

围绕真实项目,展示如何将标准、协作机制与工具链能力转化为可执行 的工程流程;并系统阐明从设计、封装、测试到制造的闭环验证体系与 量产导入路径。 > 中电标协先进封装标准分会筹建启动 中电标协将现场参与,并在启动仪式环节对协会及筹建工作作说明;同 时联合产业链各方共探先进封装标准与接口体系建设,推动标准从讨论 走向可执行、可验证的工程规则。 未曾这是不知落 C | SICA深芯盟 TrendBank Semi-insights.com 势 银 先进封装产业生态: H 从生态建设 到 应用落地 Chiplet与先进封装产业协同论坛 ई 3.26 13:30-17:30 上海浦东嘉里大酒店 五楼圆顶屋 1 论坛亮点 Q 8 首次亮相:基于典型案例沉淀的先进封装产业协同 应用解决方案 先进封装驱动产业空前"合纵连横", 从分工深化 走向协同升级 设计、制造、封测、材料设备、EDA 及应用端代表同场交流,对齐关键 需求与协作边界,降低跨环节信息偏差。通过圆桌对话与现场交流,推 动联合验证与供需对接，形成后续项目合作的具体机会。 活动议程 13:30 签到 14:00 开场&嘉宾介绍 O 大湾区先进封装创新中心筹建及 1 ...

"宁波膜智信息科技有限公司"为势银（TrendBank）唯一工商注册实体及收款账户 目以完怕. 卒丁央至余例儿证的元达到衣厂业例内 应用解决方案 围绕真实项目，展示如何将标准、协作机制与工具链能力转化为可执行 的工程流程;并系统阐明从设计、封装、测试到制造的闭环验证体系与 量产导入路径。 > 中电标协先进封装标准分会筹建启动 中电标协将现场参与,并在启动仪式环节对协会及筹建工作作说明:同 时联合产业链各方共探先进封装标准与接口体系建设,推动标准从讨论 走向可执行、可验证的工程规则。 先进封装驱动产业空前"合纵连横", 从分工深化 走向协同升级 设计、制造、封测、材料设备、EDA 及应用端代表同场交流,对齐关键 需求与协作边界,降低跨环节信息偏差。通过圆桌对话与现场交流,推 动联合验证与供需对接，形成后续项目合作的具体机会。 活动议程 13:30 签到 14:00 开场&嘉宾介绍 O 大湾区先进封装创新中心筹建及 14:05 生态建设展望 14:10 Al全球化生态对于半导体上下游的机会 O 张晟彬 - 浪潮云高级战略销售总监 14:30 待定 芯片设计企业 基于典型应用沉淀的先进封装产业 14:50 O 协同 ...

Summary of Chipone's Conference Call Company Overview - **Company**: Chipone Technology Co., Ltd. (芯原股份) - **Industry**: AI ASIC (Application-Specific Integrated Circuit) Key Points IPO and Fundraising Strategy - Chipone plans to issue up to 15% of its shares in Hong Kong, including a green shoe option, to establish an international financing platform for global marketing, key technology R&D, and potential strategic acquisitions [2][3] - The funds raised will be allocated to four main areas: R&D for key technologies, global marketing network development, strategic investments and acquisitions, and general operational funding [3][4] Market Trends and ASIC Demand - AI computing demand is shifting from training to inference and fine-tuning, with ASICs expected to see a fivefold increase in capital expenditure by 2027 [2][4] - The demand for ultra-low power small models is surging in edge AI applications, such as AR glasses and robotics, with Chipone focusing on 270M parameter-level ultra-small model applications [2][4] Design-Light Model - Chipone is promoting a "Design-Light" model to reduce operational costs for chip companies by providing IP and design services, addressing the challenges of high operational costs in traditional Fabless models [2][5] AI Development Trends - The AI industry is transitioning from a focus on large models to a combination of large and small models, emphasizing the importance of physical world interaction and understanding [6][10] - The emergence of new applications, such as AR glasses and autonomous driving, is driving the need for specialized AI chips [6][10] Collaboration with Google - Chipone is deeply integrated with Google's open-source ecosystem, supporting projects like Gemma to secure commercial opportunities and strengthen its IP position in video coding and AIGC [2][9] Domestic Market Dynamics - The domestic autonomous driving chip market is expected to see over 50% penetration of domestic solutions within three years, with Chipone addressing differentiated computing needs through a Chiplet model [2][12] ASIC Market Growth - The ASIC market is experiencing significant growth, with major players like Broadcom and Marvell reporting substantial revenue increases, indicating ASICs' critical role in the current AI wave [4][10] Future of AI and AIGC - The future of AI should not solely focus on large models; small models are equally important and can derive capabilities from larger models [10][17] - The growth of edge AI applications will drive demand for efficient, low-power AI chips, positioning Chipone favorably in the AIGC landscape [17] Conclusion - Chipone's strategic initiatives, including its IPO, focus on R&D, and collaboration with major tech players, position it well to capitalize on the growing demand for AI and ASIC technologies in various applications. The emphasis on both edge and cloud AI solutions reflects a comprehensive approach to market opportunities.

Core Insights - The article emphasizes the increasing importance of SerDes technology in AI infrastructure, highlighting its role in enhancing data exchange efficiency among GPUs and other components in large-scale systems [2][5][10] - Companies like Broadcom and Marvell dominate the ASIC design market due to their advanced SerDes capabilities, which create significant competitive advantages [6][8][9] Summary by Sections SerDes Technology - SerDes (Serializer/Deserializer) is a critical technology for high-speed data transmission, allowing for efficient chip-to-chip communication with fewer connections [4] - The evolution of SerDes from earlier standards to current high-speed versions (e.g., 224Gbps) reflects its growing significance in various applications, including AI, high-performance computing, and networking [5][6] Market Leaders - Broadcom and Marvell capture 80% of the ASIC market profits, largely due to their expertise in SerDes technology, which provides a competitive edge in connection stability [6][8] - Broadcom's Tomahawk series exemplifies high-performance SerDes integration, with the upcoming Tomahawk 6 expected to push the boundaries of data center interconnectivity [6][8] - Marvell's advancements in SerDes, particularly for Chiplet designs, position it favorably in the server and storage controller markets [7][9] Competitive Landscape - Broadcom's AI revenue is projected to reach $25 billion in 2026, while Marvell aims for over $5 billion, indicating a significant market share disparity [7][9] - New entrants like MediaTek are emerging, leveraging their SerDes technology to secure contracts with major players like Google [8][9] GPU Manufacturers - NVIDIA and AMD are also enhancing their SerDes capabilities, with NVIDIA's NVLink technology evolving to support higher bandwidths essential for AI workloads [11][12] - AMD's strategy focuses on open standards like PCIe and CXL, contrasting with NVIDIA's proprietary approach, indicating a diverse competitive landscape [12][13] Emerging Companies - New companies such as Credo, Astera Labs, and Alphawave Semi are gaining traction in the high-speed interconnect market, driven by the demand for efficient SerDes solutions [14][15][16] - Credo's focus on analog front-end optimization and Astera Labs' intelligent connectivity solutions highlight innovative approaches to address signal integrity challenges in AI data centers [15][16] Industry Trends - The shift towards 448G SerDes technology is becoming a focal point for future developments in AI infrastructure, with companies like Marvell and NVIDIA leading the charge [21][23] - The transition to optical interconnects (CPO) is anticipated as a necessary evolution to meet the demands of high-speed data transmission, further emphasizing the critical role of SerDes technology [23][24] Conclusion - The article concludes that the AI computing revolution is fundamentally tied to advancements in high-speed interconnect technology, with SerDes being a key determinant of scalability in AI systems [26]

Core Insights - The article discusses the evolution of integrated circuits (IC) driven by rapid advancements in AI computing power and increasing demand for high-bandwidth interconnects, highlighting a cyclical trend of "separation and integration" in the industry [1] Group 1: Industry Trends - The transition from single chips to larger-scale System on Chip (SoC) and then to Chiplet/multi-die configurations is emphasized as a key trend in IC development [1] - The industry is entering a post-Moore's Law phase where advanced packaging and heterogeneous integration are critical, necessitating tighter collaboration across the supply chain [1] Group 2: Collaborative Initiatives - A forum titled "From Ecological Construction to Application Landing: Chiplet and Advanced Packaging Industry Collaboration Forum" is scheduled for March 26, organized by Silicon Core Technology in collaboration with various industry stakeholders [1] - The forum aims to focus on the engineering implementation path by discussing "standards—chiplet libraries—new generation 2.5D/3D EDA toolchains" to promote a shift from "deepening division of labor" to "collaborative upgrading" [1] Group 3: Standardization Efforts - The establishment of a subcommittee for advanced packaging standards by the China Electronics Standardization Association (CESA) is set to be initiated, with participation from industry players to explore the construction of advanced packaging standards and interface systems [5] - The goal is to transition standards from discussion to executable and verifiable engineering rules [5] Group 4: Application Solutions - The article highlights the introduction of advanced packaging industry collaborative application solutions based on typical case studies, showcasing how to translate standards, collaboration mechanisms, and toolchain capabilities into executable engineering processes [4] - It also outlines a closed-loop verification system and mass production introduction path from design, packaging, testing to manufacturing [4]

Core Insights - The semiconductor industry is undergoing a structural transformation driven by unprecedented demand for computing performance, memory bandwidth, and system-level innovation due to artificial intelligence [2][3] - The industry faces significant challenges including power limitations, supply chain pressures, rising costs, and increasing technical complexity, which extend beyond traditional transistor scaling [2][3] Group 1: AI as a Structural Growth Driver - AI is fundamentally reshaping the requirements for semiconductor technology, moving beyond being just another wave of applications [2][3] - The demand for computing power, especially for large language models and generative AI systems, is growing exponentially, requiring thousands to tens of thousands of accelerators in training clusters [3][4] Group 2: Energy Efficiency as a Design Constraint - Energy efficiency has become a primary design constraint, with performance per watt now being a critical metric in the AI era [5][11] - The shift towards energy-efficient AI architectures necessitates reducing energy consumption per operation while increasing total computational throughput [5][11] Group 3: Chiplet and 3D Integration - Energy-efficient AI architectures increasingly rely on chiplet-based approaches rather than monolithic designs, allowing for optimized manufacturing of each functional module [7][9] - Recent accelerator designs, such as AMD's MI300 architecture, utilize 2.5D and 3D stacking technologies to enhance computational density and reduce energy consumption [7][9] Group 4: Process Technology and Efficiency - Despite the growing focus on packaging and architecture, process technology remains a key factor in improving energy efficiency [11][12] - Emerging device structures, like complementary FET (CFET) architecture, can potentially reduce chip-level power consumption by up to 30% [11][12] Group 5: Packaging as a Core Technology - Advanced packaging technology has evolved from a supporting role to a major performance driver, significantly enhancing energy efficiency through high-density interconnects [13][14] - 3D interconnect technologies improve efficiency, especially for AI workloads, where data transmission energy consumption is a significant portion of total power [13][14] Group 6: Interconnect and System-Level Expansion - As AI clusters scale to thousands of accelerators, system interconnect efficiency is becoming as important as chip-level performance [16][19] - The industry is exploring optical interconnects and co-packaged optical devices to reduce power consumption for long-distance data transmission [16][19] Group 7: Manufacturing Complexity and Economic Challenges - The semiconductor industry faces both technical and economic challenges, with advanced fabs requiring investments of $20 billion to $30 billion [20] - The complexity of transitioning process nodes is increasing exponentially, necessitating ecosystem coordination among hardware manufacturers, software developers, and materials suppliers [20]

Financial Data and Key Metrics Changes - Total fourth quarter revenue was $3.7 million, down 35% from Q4 2024 and up 84% from Q3 2025 [22] - New product revenue in Q4 was $2.8 million, down 39% from Q4 2024 and up 199% compared to Q3 2025 [22] - Mature product revenue was $0.9 million, down from $1 million in Q4 2024 and $1.1 million in Q3 2025 [22] - Non-GAAP gross margin in Q4 was 20.8%, impacted by inventory reserves and unexpected costs [22][23] - Non-GAAP net loss was $2.9 million or $0.17 per share, compared to a net income of $0.6 million or $0.04 per share in Q4 2024 [24] Business Line Data and Key Metrics Changes - The company is focusing on high-density eFPGA hard IP cores and expects significant revenue contributions from its storefront business model starting in 2026 [7][9] - The company has received orders for its SRH FPGA dev kit, indicating strong demand for its products [9] Market Data and Key Metrics Changes - The company is positioned to address both discrete and embedded FPGA designs across a full spectrum of radiation hardness requirements, leveraging its SRH FPGA test chip [11][14] - The company anticipates a mature product revenue of approximately $4 million for the full year 2026 [25] Company Strategy and Development Direction - The company plans to conduct three multi-project wafer (MPW) tape-outs in 2026, with costs covered by customer contracts [33] - The company is expanding its involvement with defense contractors and exploring opportunities in commercial markets [16][66] - The company aims to achieve between 50% and 100% revenue growth in 2026, supported by a solid foundation of government contracts and pending agreements [34] Management's Comments on Operating Environment and Future Outlook - Management acknowledged that 2025 revenue was lower than expected due to contract delays but expressed confidence in achieving nearly 50% sequential revenue growth in Q1 2026 [7] - Management expects evaluations of test chips to occur in 2026, with actual development activities starting in the following year [46] - The company anticipates cash flow positivity in the second half of 2026, with net income also expected to improve during that period [48][51] Other Important Information - The company took a large impairment charge on SensiML due to accounting practices, and discussions for divestiture are ongoing [20][21] - The company is working to secure a new banking partner to obtain more favorable terms and reduce its line of credit [31] Q&A Session Questions and Answers Question: Can you provide insights on the expected dollar growth from 2025 to 2026? - Management indicated that $4 million will come from the base mature business, with additional contributions expected from government contracts and IP licenses [40][41] Question: What is the expected timing for wins with defense industrial bases (DIBs)? - Management expects evaluations to take place this year, with architecture understanding by the end of the fiscal year, leading to development activities next year [46] Question: Will the company be net income positive this year? - Management expects to be cash flow positive in the second half of the year, with net income also anticipated to improve during that period [48][51] Question: Can you elaborate on the dynamics of the three MPWs planned for this year? - Management confirmed that two of the MPWs will be fully covered by customer contracts, with the third partially covered [53] Question: What is the competitive landscape for the company's products? - Management highlighted that the company is well-positioned in the market, particularly in the radiation-hardened FPGA space, with limited competition from U.S.-based companies [66][68]

Financial Data and Key Metrics Changes - Total fourth quarter revenue was $3.7 million, down 35% from Q4 2024 and up 84% from Q3 2025 [22] - New product revenue in Q4 was $2.8 million, down 39% from Q4 2024 and up 199% compared to Q3 2025 [22] - Mature product revenue was $0.9 million, down from $1 million in Q4 2024 and $1.1 million in Q3 2025 [22] - Non-GAAP gross margin in Q4 was 20.8%, impacted by inventory reserves and unexpected costs [22][23] - Non-GAAP net loss was $2.9 million or $0.17 per share, compared to a net income of $0.6 million or $0.04 per share in Q4 2024 [24] Business Line Data and Key Metrics Changes - The company is focusing on high-density eFPGA hard IP cores and expects significant revenue contributions from its storefront business model starting in 2026 [7][8] - The company has received orders for its SRH FPGA dev kit, indicating strong demand for its test chips [9][10] Market Data and Key Metrics Changes - The company is positioned to address both discrete and embedded FPGA designs across a full spectrum of radiation hardness requirements, expanding its serviceable addressable market (SAM) [11][14] - The company anticipates a mature product revenue of approximately $4 million for the full year 2026 [25] Company Strategy and Development Direction - The company plans to conduct three multi-project wafer (MPW) tape-outs in 2026, with costs covered by customer contracts [33] - The company is leveraging architectural enhancements to address lucrative markets for very high-density eFPGA cores in ASIC designs [14][33] - The company is exploring the potential to leverage FPGA as a chiplet co-packaged with microcontrollers, indicating a strategic move towards chiplet technology [17][18] Management's Comments on Operating Environment and Future Outlook - Management expressed confidence in achieving 50% to 100% revenue growth in 2026, supported by a solid foundation from government contracts and pending contracts in negotiation [34] - The company expects to be cash flow positive in the second half of the year, with net income also anticipated to be positive during that period [48][51] Other Important Information - The company took a large impairment charge on SensiML due to accounting practices, but is in discussions for potential divestiture [20][21] - The company is working to secure a new banking partner to obtain more favorable terms and reduce its line of credit [31] Q&A Session Summary Question: Can you provide insights on the expected dollar growth from 2025 to 2026? - Management indicated that $4 million will come from the base mature business, with additional contributions expected from government contracts and IP licenses [40][41] Question: What is the expected timing for wins with DIBs? - Management expects evaluations to take place this fiscal year, with actual development activity starting next year [46] Question: Will the company be net income positive this year? - Management expects to be net income positive in the second half of the year [51] Question: Can you clarify the dynamics of the three MPWs planned for this year? - Management confirmed that two of the MPWs will be fully covered by customer contracts, with the third partially covered [53] Question: What is the trajectory of gross margins through the year? - Management anticipates Q1 gross margins around 45%, with potential increases in Q3 and Q4 [98]

Financial Data and Key Metrics Changes - Total fourth quarter revenue was $3.7 million, down 35% from Q4 2024 and up 84% from Q3 2025 [24] - New product revenue in Q4 was $2.8 million, down 39% from Q4 2024 and up 199% compared to Q3 2025 [24] - Mature product revenue was $0.9 million, down from $1 million in Q4 2024 and $1.1 million in Q3 2025 [24] - Non-GAAP gross margin in Q4 was 20.8%, impacted by inventory reserves and unexpected costs [24][25] - Non-GAAP net loss was $2.9 million or $0.17 per share, compared to a net income of $0.6 million or $0.04 per diluted share in Q4 2024 [26] Business Line Data and Key Metrics Changes - The company is focusing on both new and mature products, with new product revenue showing significant growth compared to the previous quarter [24] - The company has received orders for its SRH FPGA dev kit, indicating strong demand for its new products [9] Market Data and Key Metrics Changes - The company is positioned to benefit from contracts with the U.S. government, with a potential expansion of its contract to $89 million [34] - The company is also exploring opportunities in the commercial sector, with a focus on non-defense applications [65] Company Strategy and Development Direction - The company plans to accelerate its storefront business model in 2026, with three multi-project wafer (MPW) tape-outs planned [35] - Architectural enhancements have been developed to address lucrative markets for very high-density eFPGA cores [36] - The company aims to deliver between 50% and 100% revenue growth in 2026, supported by a solid foundation of government contracts and mature business [36] Management's Comments on Operating Environment and Future Outlook - Management acknowledged that 2025 revenue was lower than expected due to contract delays but expressed confidence in achieving nearly 50% sequential revenue growth in Q1 2026 [6] - The company expects evaluations to take place this year with defense industry buyers, leading to potential development activity next year [47] - Management anticipates cash flow positivity in the second half of the year, with net income also expected to improve during that period [50][51] Other Important Information - The company took a large impairment charge on SensiML due to accounting practices related to assets held for sale [21] - The company is in discussions with potential buyers for SensiML, focusing on AI and drone projects [22] Q&A Session Summary Question: Can you provide insights on the expected dollar growth from 2025 to 2026? - Management indicated that $4 million will come from the base mature business, with additional revenue expected from government contracts and IP licenses [42] Question: What is the expected timing for wins with defense industry buyers? - Management expects evaluations to occur this year, with development activity starting next year [47] Question: Will the company be net income positive this year? - Management expects to be cash flow positive in the second half of the year, with net income also anticipated to improve during that period [50][51] Question: Can you elaborate on the three MPWs planned for this year? - Management confirmed that two of the MPWs will be fully covered by customer contracts, with the third partially covered [55] Question: What is the competitive dynamic for the company's products? - Management highlighted that the company is well-positioned in the market, particularly in the defense sector, with few competitors meeting the same radiation hardness requirements [68]