如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容 编译自 NRC 。 如何粉碎一块薄饼？这个问题困扰着阿姆斯特丹纳米光刻高级研究中心 (ARCNL) 的研究员迪翁· 恩格尔斯 (Dion Engels)。 这里所说的薄饼指的是被粉碎的锡滴，它在 ASML 的光刻机中每秒被引爆五万次。这会产生等离 子体，发射出极紫外 (EUV) 光：一种极紫外辐射，将高度精细的芯片图案投射到硅片或晶圆上。 集成的晶体管越多，芯片的性能就越强。得益于 EUV 光刻机，如今用于手机或人工智能数据中心 的最先进处理器上的芯片设计线间距仅为几十纳米——百万分之一毫米。 ASML 与美国 Cymer 实验室合作研究 EUV 技术长达二十年，发现粉碎锡滴可以产生更多的 EUV 光。其结果是：生产英伟达、苹果、三星或英特尔先进芯片的机器很快就会更加高效地运转。 ASML 系统的许多基础设计都诞生于阿姆斯特丹东区的科学园。ARCNL 成立于十年前，与阿姆 斯特丹大学合作成立。其推动力来自 ASML 的技术总监兼联席总裁 Martin van den Brink，他于 去年退休。ARCNL 承担 ASML 三分之一的预算（每年约 400 万 ...

公众号记得加星标⭐️，第一时间看推送不会错过。 来源：内容 编译自 NRC 。 如何粉碎一块薄饼？这个问题困扰着阿姆斯特丹纳米光刻高级研究中心 (ARCNL) 的研究员迪翁·恩 格尔斯 (Dion Engels)。 这里所说的薄饼指的是被粉碎的锡滴，它在 ASML 的光刻机中每秒被引爆五万次。这会产生等离子 体，发射出极紫外 (EUV) 光：一种极紫外辐射，将高度精细的芯片图案投射到硅片或晶圆上。 集成的晶体管越多，芯片的性能就越强。得益于 EUV 光刻机，如今用于手机或人工智能数据中心的 最先进处理器上的芯片设计线间距仅为几十纳米——百万分之一毫米。 ASML 与美国 Cymer 实验室合作研究 EUV 技术长达二十年，发现粉碎锡滴可以产生更多的 EUV 光。其结果是：生产英伟达、苹果、三星或英特尔先进芯片的机器很快就会更加高效地运转。 芯片元件尺寸缩小的速度正在放缓，因为芯片设计变得越来越高：制造商正在将芯片元件粘合在一 起，并想出更智能地排列晶体管的方法，例如从底部供电。 ASML 系统的许多基础设计都诞生于阿姆斯特丹东区的科学园。ARCNL 成立于十年前，与阿姆斯特 丹大学合作成立。其推动力来自 AS ...

Core Insights - The article discusses the critical challenges faced by photomasks in the development of lithography technology, particularly as the industry transitions to EUV (Extreme Ultraviolet) and beyond, highlighting the high costs associated with photomask manufacturing and maintenance [1][2][3]. Group 1: EUV and Non-EUV Challenges - The primary challenge for EUV is the high cost of manufacturing, maintaining, and replacing masks, which significantly impacts the overall production costs [1][3]. - Non-EUV applications are also facing similar challenges, as companies aim to stay competitive while managing costs associated with advanced photomask technologies [2][3]. - The lifespan of EUV photomasks is notably shorter compared to DUV (Deep Ultraviolet) masks, leading to increased cleaning frequency and the need for backup masks, which further escalates costs [3][4]. Group 2: Multi-Exposure Techniques - Multi-exposure techniques are deemed necessary for the future of EUV lithography, as they will enhance resolution and pattern fidelity [6][7]. - Companies are actively researching multi-exposure methods to extend the lifespan of EUV technology, with Intel planning to use high-NA EUV for its 14A node due to single-exposure limitations [7][8]. - The industry is exploring various techniques to optimize multi-exposure applications, although challenges remain in terms of cost and complexity [8][9]. Group 3: Photomask Materials and Process Control - The evolution of photomask materials is crucial for supporting finer nodes, with advancements in binary reflective masks and low-refractive-index reflective masks improving image contrast [10][11]. - The introduction of metal oxide resists is highlighted as a significant advancement, offering higher contrast and better etch resistance compared to traditional resists [11][12]. - Customization of mask blank properties presents opportunities for enhancing wafer process margins, although the market for new resist materials remains niche and underdeveloped [11][12]. Group 4: EUV Membrane Challenges - EUV membranes face challenges related to transmission rates and durability, with current membranes requiring frequent replacements that increase costs and downtime [14][15]. - The complexity of EUV membranes compared to 193i membranes complicates the cleaning and replacement processes, impacting throughput and efficiency [15][16]. - Ongoing research into alternative membrane materials, such as carbon nanotube-based versions, shows promise but faces reliability and performance challenges [15][16].