Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. is on the verge of an IPO on the Sci-Tech Innovation Board, leveraging its advanced packaging technologies to achieve significant financial growth, but it faces structural risks including high customer concentration, sustainability of R&D investments, and investor protection challenges as a red-chip enterprise [2][3][4]. Customer Concentration Risks - The company has a high and increasing customer concentration, with the top five customers accounting for 72.83% of sales in 2022, rising to 90.87% by mid-2025 [4][16]. - The reliance on the largest customer has escalated from 40.56% in 2022 to 74.4% in mid-2025, indicating that over 70% of revenue and most profits are tied to a single client [4][16]. - This extreme dependency poses multiple risks, including operational stability, limited bargaining power, and financial health concerns due to low accounts receivable turnover [17][18]. R&D Investment and Sustainability Challenges - Despite rapid revenue growth, the company's R&D expenditure as a percentage of revenue has decreased from 15.72% in 2022 to 11.11% by mid-2025, raising concerns about the sustainability of its technological leadership [20]. - The number of R&D personnel has also declined, from 734 in 2023 to 663 in mid-2025, further questioning the company's core competitiveness [20][21]. - The company faces intense competition from global giants like TSMC and Intel, which invest significantly more in R&D, potentially jeopardizing Shenghe Jingwei's technological advantages [21]. Investor Protection Issues - As a red-chip enterprise registered in the Cayman Islands, Shenghe Jingwei faces inherent challenges in investor protection due to differences in legal frameworks compared to domestic companies [22][23]. - The complex corporate structure, involving multiple legal entities, complicates the realization of investor rights, such as dividends and participation in major decisions, increasing potential difficulties in exercising rights [23][24]. - The differences in shareholder rights and legal processes may hinder the ability of small investors to effectively monitor and protect their interests [22][23].

Core Insights - HBM technology is evolving towards higher stacking layers, with a clear progression from 4 layers to 8, 12, and now approaching 16 layers, enhancing capacity and bandwidth for AI GPUs [1] - The introduction of 16-layer HBM4 by SK Hynix marks a significant milestone, with a single stack capacity of 48GB [1] - The industry is divided between those pursuing revolutionary changes and those advocating for practical improvements [2] Group 1: HBM Technology Evolution - HBM's evolution is characterized by increasing stacking layers, with 8 layers being the most common configuration for AI GPUs due to stable yield and mature supply chains [1] - The transition to 12 layers has become the main production direction in recent years, balancing capacity, performance, and cost effectively [1] - The recent CES 2026 showcased the world's first 16-layer HBM4 sample, indicating the industry's readiness for higher stacking [1] Group 2: Hybrid Bonding and Fluxless Technology - Hybrid bonding is a cutting-edge interconnection technology that eliminates solder and flux, achieving closer to direct connections with higher I/O density [3] - The recent JEDEC revision allows for a height increase in HBM modules, providing more space for traditional micro-bump technology, which may delay the commercial debut of hybrid bonding [5] - Fluxless technology is emerging as a transitional solution, addressing the challenges of traditional interconnection methods in the context of 16-layer HBM production [7][11] Group 3: Industry Players and Strategies - SK Hynix remains cautious about adopting Fluxless technology for HBM4, opting to continue with its Advanced MR-MUF process, which has proven effective in previous generations [16][19] - BESI is positioned as a proponent of hybrid bonding, focusing on refining technology and market strategies to prepare for future demands [23] - ASMPT emphasizes the importance of TCB as the core platform for HBM stacking, advocating for Fluxless approaches to enhance production stability and yield [24][25] Group 4: Market Dynamics and Future Outlook - The relaxation of HBM4 height standards has extended the lifecycle of micro-bump technology, impacting the competitive landscape among equipment suppliers [22] - The ongoing patent disputes between Hanmi Semiconductor and Hanwha highlight the competitive tensions within the supply chain for HBM technology [27][26] - The industry is likely to see a gradual integration of hybrid bonding rather than an abrupt shift, as companies balance performance and yield in their production strategies [29]

Core Viewpoint - The evolution of HBM technology is characterized by increasing stack heights, enhancing capacity and bandwidth, which is crucial for AI GPUs due to their need for high data feeding speeds [1]. Group 1: HBM Technology Development - HBM has progressed from 4 layers to 8 layers, 12 layers, and is approaching 16 layers, with 8 layers being the most common configuration for AI GPUs [1]. - The introduction of 16-layer HBM4 has been showcased by SK Hynix, with a single stack capacity of 48GB [1]. - Increasing the number of layers significantly raises manufacturing challenges, including precision in mounting, solder joint spacing, and reliability issues [1]. Group 2: Hybrid Bonding and Fluxless Technology - Hybrid bonding is a cutting-edge interconnection technology that eliminates solder and flux, aiming for direct connections with higher I/O density [4]. - The recent JEDEC revision allows for a height increase in HBM modules, providing more space for traditional micro-bump technology [6]. - Fluxless technology is emerging as a transitional solution to address the limitations of traditional interconnection methods, particularly in high-density applications [8][12]. Group 3: TCB and Its Variants - Thermal Compression Bonding (TCB) is a key method for HBM stacking, allowing for higher interconnect density and precision [9][10]. - TCB has various types, including TC-CUF, TC-MUF, TC-NCP, and TC-NCF, each addressing specific challenges in high-density applications [12]. - The industry is moving towards Fluxless TCB to mitigate issues related to solder residues and improve yield and reliability [12][13]. Group 4: Industry Perspectives and Equipment Suppliers - SK Hynix remains cautious about adopting Fluxless technology for HBM4, preferring to continue with its Advanced MR-MUF process [19][21]. - BESI is seen as a proponent of hybrid bonding, focusing on preparing for future demands while facing short-term challenges due to slower-than-expected adoption rates [24]. - ASMPT emphasizes TCB as the core platform for HBM stacking, particularly during the transition from 12 to 16 layers, while also pushing for Fluxless advancements [25][26]. Group 5: Competitive Landscape - Hanmi Semiconductor is positioned as a key player in the "improvement route," optimizing TCB equipment for SK Hynix's processes [27]. - Hanwha Precision Machinery is emerging as a competitor, developing TCB equipment and exploring Fluxless technology to disrupt the existing supply chain [28]. - Kulicke & Soffa (K&S) is recognized for its stability and large-scale manufacturing experience, serving as a foundational player in the industry [29]. Conclusion - The delay in Fluxless technology adoption highlights the complexities of advanced packaging, emphasizing the need for a balance between innovation and production stability [31].

Core Viewpoint - The article discusses the challenges faced by Rapidus in achieving its ambitious goals in the semiconductor industry, particularly in the context of AI chip production and the transition to 3D IC technology. Group 1: Rapidus and AI Chip Production - Rapidus is focusing on advanced packaging technologies to secure orders from major clients like GAFAM in the growing AI market [4][8] - The company aims to mass-produce 2nm chips by 2027, but there are doubts about its capability to achieve this in the front-end process [7][8] - The article argues that Rapidus's goal of ultra-short turnaround time (TAT) for AI chip packaging is unrealistic due to various technological and supply chain challenges [71] Group 2: Transition to 3D IC Technology - The semiconductor industry is experiencing a paradigm shift from front-end processing to back-end 3D IC technology, which integrates multiple chips into a single package [29][31] - This shift is driven by the limitations of traditional scaling methods and the need for higher performance in AI applications [26][29] - Rapidus's entry into the 3D IC field aligns with industry trends, but achieving its goals will require overcoming significant hurdles [31][71] Group 3: Challenges in HBM Production - The production of High Bandwidth Memory (HBM) is a bottleneck for AI chip manufacturing, with a lead time of approximately six months [67] - HBM production is complex and costly, with a significantly lower yield compared to standard DRAM, making it a critical factor for companies like Rapidus [66][67] - The current market for advanced HBM is dominated by suppliers like SK Hynix, which has sold out its 2025 production capacity, further complicating Rapidus's plans [68][71]