Core Viewpoint - The semiconductor industry is developing a new type of High Bandwidth Memory (HBM) called SPHBM4, which aims to reduce design complexity and manufacturing costs while maintaining performance similar to existing HBM products. This development could significantly impact companies like Samsung Electronics and SK Hynix, as well as the broader ecosystem including TSMC and NVIDIA [3][6]. Group 1: SPHBM4 Development - JEDEC is in the final stages of developing the SPHBM4 standard, which utilizes the same DRAM as HBM4 but serializes I/O pins at a 4:1 ratio, reducing the number of I/O pins from 1024 to 512 while still supporting the same bandwidth [3][4]. - The SPHBM4 standard is expected to be released in the coming months, according to Eliyan, a U.S. semiconductor startup that supports the new standard [4][5]. Group 2: Technical Aspects - SPHBM4's performance relies on stable interconnect technology that can achieve over four times the transmission speed per I/O pin, which is crucial for its operation [4]. - The introduction of SPHBM4 will necessitate a redesign of the substrate chip responsible for memory controller functions, as the I/O pin count will be significantly reduced [5]. Group 3: Packaging and Cost Implications - The intermediary layer, which connects HBM and the printed circuit board (PCB), can simplify connections due to the reduced number of I/O pins, allowing for the use of organic intermediary layers instead of more expensive silicon layers [5]. - The adoption of organic intermediary layers is expected to lower packaging manufacturing costs while allowing for more flexible designs, potentially increasing overall storage capacity [5]. Group 4: Market Uncertainty - The commercialization of SPHBM4 remains uncertain, as the standard is still under development and may undergo changes or even be rejected by the JEDEC board [6]. - Major tech companies are currently focused on enhancing both the speed and density of HBM, indicating that SPHBM4 may be one of several attempts to reduce manufacturing costs for AI accelerators based on HBM technology [6].

公众号记得加星标⭐️，第一时间看推送不会错过。 JEDEC——负责制定业界标准内存规格的组织——正接近完成 SPHBM4 的制定。这是一种新的内存 标准，目标是在采用"较窄"的 512 位接口的情况下，提供完整的 HBM4 级带宽，同时实现更高的容 量，并通过兼容传统有机基板来降低集成成本。如果这一技术顺利落地，它将填补 HBM 可服务市场 中的诸多空白；但正如我们下文将解释的那样，它不太可能成为 GDDR 内存的终结者。 尽管采用 1024 位或 2048 位接口的高带宽存储（HBM）在性能和能效方面无可匹敌，但如此宽的接 口会占用高端处理器内部大量宝贵的硅面积。这限制了单颗芯片上可集成的 HBM 堆栈数量，从而约 束了 AI 加速器所支持的内存容量，进而影响单个加速器的性能，以及基于这些加速器构建的大规模 集群的整体能力。 "标准封装"中的 HBM 标准封装高带宽存储（SPHBM4）正是为了解决这一问题而提出的。它将 HBM4 的内存接口宽度从 2048 位缩减至 512 位，并通过 4:1 串行化来维持相同的总带宽。JEDEC 并未明确说明所谓的"4:1 串行化"是指将 HBM4 的数据传输速率从 8 ...