Core Viewpoint - The development of High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography technology is gaining momentum, showcasing significant potential in size reduction, process simplification, and design flexibility, driven by a collaborative ecosystem involving leading chip manufacturers and suppliers [2][19]. Group 1: Resolution and Image Contrast - High NA EUV lithography, with a numerical aperture (NA) of 0.55, offers a 67% increase in resolution compared to 0.33 NA EUV, enabling the ability to resolve features as small as 16 nanometers [4][5]. - The resolution of lithography systems is influenced by factors such as the k1 factor, wavelength of light, and the NA of the projection lens, with the goal of achieving a k1 value close to its physical limit of 0.25 [4]. Group 2: Process Simplification - High NA EUV lithography reduces the need for complex multiple exposure steps, allowing for the printing of minimum chip feature sizes in a single exposure, which enhances manufacturing efficiency and reduces costs [10][19]. - For critical metal layers in advanced logic nodes, High NA EUV lithography can achieve the required specifications in a single exposure, while 0.33 NA EUV requires multiple masks [11]. Group 3: Design Flexibility - The advancements in High NA EUV lithography allow for the reapplication of 1.5D and 2D Manhattan designs, enabling greater design flexibility and potentially reducing chip area and costs [16][18]. - The technology supports the introduction of complex curved geometries in chip design, which can lead to significant area reductions and improved performance [18]. Group 4: Industry Implications - High NA EUV lithography is positioned as a critical technology for future advancements in AI chips, high-performance computing, and next-generation memory, addressing the rapid hardware development needs of these applications [19]. - The technology is also essential for meeting the goals outlined in the European Chips Act regarding the advancement of logic technology nodes below 2 nanometers [19].

如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容 编译自 sedaily ，谢谢 。 三星电子已确定了三年内量产垂直通道晶体管（VCT）DRAM（即所谓的下一代存储器）的路线 图。竞争对手公司SK海力士这被解读为蕴含着提前一代成功实现量产、挽回"超级差距"地位的意 志。 据业内人士27日透露，三星电子半导体（DS）部门管理层已经敲定了这一路线图，并已开始认真 开展该产品的量产工作。 VCT DRAM是指存储元件中控制电流流动的晶体管垂直排列的产品。它被认为是一个"游戏规则改 变者"，通过放置比现有平放方法更多的晶体管，可以实现高容量。但这种方法比现有工艺要困难 和复杂得多。突破技术壁垒并不容易，因为它不仅需要制造存储器件的前期工艺，还需要现有 DRAM工艺中未曾用到的先进封装工艺。 三星电子目前正在量产10㎚（纳米，十亿分之一米）级第五代DRAM，并计划今年量产第六代。 在确定明年开发第 7 代 DRAM 的计划后，该公司对第 8 代 (1e) DRAM 和全新方法 VCT DRAM 进行了权衡，最终决定采用 VCT DRAM 方法。据悉，SK海力士已制定了第七代→1nm级第一代 （0a）→垂直DRAM（ ...