传统封装

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一文看懂芯片的封装工艺(传统封装篇)
芯世相· 2025-05-30 09:47
Core Viewpoint - The article provides a detailed overview of the traditional packaging process in semiconductor manufacturing, highlighting the various steps involved and the technologies used in each stage. Group 1: Traditional Packaging Process - The traditional packaging process begins with thinning the wafer, reducing its thickness from 600-800μm to tens to a hundred μm for better heat dissipation and electrical performance [8][9]. - Cutting the wafer involves applying a protective blue film and using advanced techniques like laser cutting, which offers higher precision compared to mechanical cutting [10][11]. - The die attach process connects the die to the substrate using various methods, including adhesive bonding, soldering, and eutectic bonding, with epoxy resin being a common adhesive [13][14][16]. Group 2: Electrical Connection and Testing - Wire bonding is used to establish electrical connections between the die and the substrate, utilizing materials like gold, silver, copper, and aluminum [19][17]. - After bonding, the components undergo cleaning and inspection, often using Automatic Optical Inspection (AOI) for high efficiency and defect detection [21][24][25]. - The final steps include molding, de-flashing, post-mold curing, and final testing to ensure the functionality and quality of the packaged chips before shipping [28][36][37]. Group 3: Packaging Materials and Techniques - Packaging can be categorized into plastic, ceramic, and metal types, with plastic packaging being the most common due to its cost-effectiveness and lightweight properties [28]. - The use of epoxy molding compound (EMC) is prevalent in plastic packaging, providing protection against environmental factors [28]. - The process also includes the application of solder balls for BGA packaging and the use of lead-free plating to meet regulatory standards [33][34].
2025年中国半导体先进封装市场研读:后摩尔时代,先进封装引领半导体创新趋势
Tou Bao Yan Jiu Yuan· 2025-05-20 12:16
Investment Rating - The report does not explicitly state an investment rating for the semiconductor advanced packaging industry Core Insights - Advanced packaging technology is a critical link between chip design and application, significantly enhancing chip performance and reducing power consumption while alleviating constraints in high-end chip manufacturing processes [2] - The Chinese government places high importance on the development of the semiconductor industry, implementing various policies to support independent innovation and technological breakthroughs [2] - The advanced packaging market is expected to grow rapidly, with China's packaging market projected to reach 355.19 billion yuan by 2025, with advanced packaging accounting for 32% of the market [45][47] Summary by Sections Overview of the Semiconductor Packaging Industry - Packaging is a core process in semiconductor manufacturing, involving the placement, fixation, sealing of chips, and connecting chip contacts to the package shell [14][18] - The development of semiconductor packaging technology can be divided into four stages, with the current stage being advanced packaging [19][21] Advanced Packaging Technology Types - The global advanced packaging market includes IDM, Foundry, and OSAT manufacturers, with leading companies adopting a "large platform + technology branch" architecture [4][51] - Major OSAT manufacturers in China have formed industrial capabilities through independent research and acquisitions, covering a wide range of applications from consumer electronics to AI chips [7] Market Dynamics - The global packaging testing market is expected to grow from $51 billion in 2016 to $72.27 billion by 2025, with advanced packaging projected to capture half of the market share [47] - China's packaging testing market is growing at a compound annual growth rate (CAGR) of 12.54%, significantly higher than the global market's 3.89% [47] Importance of Advanced Packaging - Advanced packaging is essential for integrating multiple functions within a system, enhancing overall system performance beyond the limitations of Moore's Law [35][38] - The report highlights that advanced packaging can improve chip performance without shrinking process nodes, addressing the rising costs associated with advanced process development [39][44]