Core Viewpoint - Chiplet technology is a method to meet the growing demands for computing power and I/O bandwidth by splitting SoC functions into smaller heterogeneous or homogeneous chips, integrated into a single system-in-package (SIP) [1] Group 1: System Partitioning - Design teams must consider which functional blocks to include and how to partition these functions across different chipsets, while also selecting the most efficient semiconductor process node for each functional block [2] - Common high-level partitioning schemes may involve separating compute chips, I/O chips, and storage functions into different chipsets, weighing factors like latency, bandwidth, and power consumption based on the chosen process nodes and partitioning [2] Group 2: Process Node Selection - In the latest process nodes, AI accelerators may be ideal for optimizing performance and power, but implementing cache at this node may not be efficient; SRAM is better implemented at lower-cost nodes [3] - A 3D implementation can be considered, where compute chips are on the latest node and SRAM and I/O are on older nodes, exemplified by AMD's Ryzen 7000X3D processor with second-generation 3D V-Cache [3] Group 3: Chip-to-Chip Connection Considerations - UCIe has become the de facto standard for die-to-die connections, with design teams needing to understand bandwidth requirements based on workload, including both data and control bandwidth [4] - Designers have various options for data rates and configurations, needing to balance data rates (ranging from 16G to 64G) and the number of channels to meet chip constraints [4] Group 4: Advanced Packaging Challenges - The focus on packaging technology has intensified, presenting both opportunities and challenges in multi-chip designs [6] - Designers must decide how to interconnect chips in multi-die designs, with considerations for cost, design speed, and interconnect density [6][7] Group 5: Testing and Security Design - Testing planning involves wafer probing to provide known good die (KGD) and using protocols like IEEE 1838 for accessing chips that may not be directly accessible [9] - Security design considerations arise with IP integration, requiring authentication features and potential support for secure computing architectures to protect sensitive data [10]

Group 1: Financial Forecasts - Major companies in the multi-modal AI sector are expected to report significant growth in net profits for 2023, with Dainian Co. projected to have a lower limit of 7.37 billion yuan and a growth rate of 217% [1] - Other notable forecasts include Hengsheng Electronics with a net profit of 1.344 billion yuan and a growth rate of 23%, and Keda Xunfei with a net profit range of 645 million to 730 million yuan, reflecting a growth rate between 15% and 30% [1] - Companies like Vision China and Chinese Online are also expected to show positive growth, while several firms, including Tuoerli and Juechada, are projected to report losses [1] Group 2: Market Demand Background - The IC suppliers in Shenzhen are facing unprecedented delivery pressures due to explosive growth in smart wearable devices and IoT terminals by 2025 [1] - Common industry pain points include delivery delays causing production line stoppages and smaller clients being squeezed out by larger manufacturers [1] - A specific case highlighted a drone startup that had to delay a product launch by three months due to waiting for a microcontroller unit (MCU) [1] Group 3: Product and Technology Overview - Current mainstream demand is focused on three types of chips: low-power Bluetooth SoCs for smartwatches and AR glasses, edge computing AI acceleration chips for localized data processing, and highly integrated PMICs for multi-voltage systems [1] - These chips are primarily manufactured using 28nm to 12nm process nodes and utilize Chiplet designs to reduce development costs [1] - An example of innovation includes a domestic RISC-V chip that has achieved a 40% improvement in energy efficiency through dynamic voltage frequency adjustment technology [1] Group 4: Supply Chain Solutions - To address market fluctuations, a three-tier defense system is recommended: channel verification mechanisms, safety stock strategies maintaining 6-8 weeks of rolling inventory, and pre-research on alternative solutions [2] - A specific case of a medical device manufacturer successfully reducing BOM shortage rates from 12% to below 3% through strategic supply chain management is noted [2] Group 5: Industry Competitive Landscape - The IC design industry is characterized by strong specialization and numerous sub-markets, with significant technical barriers between different segments [4] - Smaller companies typically focus on specific sub-markets to build technical barriers and product advantages, while larger traditional firms leverage their resources for rapid technology accumulation and product promotion [4] - This results in a competitive landscape where both large manufacturers and small enterprises coexist [4] Group 6: Company Profiles - Chip Origin Co., established in 2001, provides comprehensive IC customization services and semiconductor IP licensing, focusing on advanced chip design capabilities [6] - Guoxin Technology, also founded in 2001, specializes in embedded CPU technology and aims to support national strategic needs in information security and automotive electronics [6] - Chuangji Technology, established in 2006, focuses on the development and sales of communication core chips, providing application solutions and technical support [6]

Core Viewpoint - Intel has made significant advancements in chip packaging technology under the leadership of new CEO Chen Liwu, particularly with the introduction of the EMIB-T technology, which enhances chip packaging size and power delivery capabilities to support new technologies like HBM4/4e [1][9]. Group 1: EMIB-T Technology Advancements - EMIB-T integrates TSV (Through-Silicon Via) for vertical signal transmission between chips, reducing power transmission resistance by over 30%, which minimizes voltage drop and signal noise [2][6]. - The technology incorporates high-density MIM (Metal-Insulator-Metal) capacitors to suppress power noise, ensuring signal integrity, especially in high-performance applications like AI accelerators and data center processors [2][7]. - EMIB-T supports a maximum package size of 120x180 mm, allowing integration of over 38 bridges and 12 dies, with plans to reduce bump pitch from 45 microns to as low as 25 microns in the future [2][7]. Group 2: Strategic Importance and Market Position - Intel's foundry aims to leverage cutting-edge process node technologies to manufacture chips for both internal and external clients, enhancing performance, cost, and energy efficiency through complex heterogeneous designs [4][5]. - The EMIB-T technology is crucial for supporting HBM4 memory and UCIe interconnect requirements, making it an ideal packaging solution for AI accelerators, data center processors, and supercomputing chips [7][8]. - Intel plans to achieve mass production of EMIB-T packaging by the second half of 2025, with a vision to integrate over 24 HBM chips in a single package by 2028, significantly impacting global semiconductor packaging technology [9].

Core Viewpoint - The U.S. government's restrictions on EDA tools from major suppliers like Siemens, Synopsys, and Cadence pose significant challenges for China's high-end chip design industry, particularly for advanced processes below 3nm [2][3]. Group 1: EDA Market Overview - EDA (Electronic Design Automation) is essential for chip design, covering the entire process from logic simulation to physical verification and layout design [3]. - The global EDA market is dominated by three major players: Synopsys, Cadence, and Siemens EDA, which together hold over 80% market share, while China's domestic market penetration is less than 12% [3]. - The cost of designing a 5nm chip using international tools is approximately $40 million, but without these tools, costs could soar to $7.7 billion, highlighting the critical role of EDA tools in chip design [3]. Group 2: Domestic EDA Companies - Huada Jiutian (301269.SZ) is a leader in analog circuit design, achieving a revenue of 1.01 billion yuan in 2023, a 26.6% year-on-year increase, and holds the largest market share among domestic companies [4][5]. - Gekun Electronics (688206.SH) specializes in device modeling and simulation, achieving international standards in SPICE simulation, with a revenue share of 30% from design-related EDA in 2023 [6]. - Guangli Micro (301095.SZ) focuses on yield analysis and manufacturing EDA, with over 80% of its business in testing equipment and a 34.3% year-on-year growth in software development and licensing in 2023 [7][8]. Group 3: Paths for Domestic EDA Breakthrough - Domestic EDA companies are pursuing three main strategies to overcome external restrictions: integrating AI with EDA tools, advancing Chiplet and packaging technologies, and fostering open-source ecosystems and international collaborations [10][11]. - Huada Jiutian has launched a 3DIC Chiplet design platform and is collaborating with Changjiang Electronics to develop domestic packaging EDA solutions [10]. - Companies like Gekun Electronics and Xinhua Zhang are working with international firms like Samsung and SK Hynix to mitigate technology isolation risks [12]. Group 4: Industry Outlook - The domestic EDA market is expected to exceed 20 billion yuan in the next three years, with an annual growth rate of 18.7%, potentially increasing the domestic market share to 25% by 2025 [13]. - Key technical focuses include integrating full-process platforms and developing independent PDKs in collaboration with major foundries like SMIC and Changjiang Storage [14][15]. - The education sector is responding to industry needs by establishing new "Integrated Circuit EDA" programs, aiming to train over 5,000 professionals annually [16].