如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容来自 Source：moneyDJ ，谢谢 。 FOPLP(面板级扇出型封装)成为新的先进封装竞逐市场，封测大厂力成(6239)执行长谢永达昨(29) 日于法说会上透露，公司正与一家美国客户合作验证中，即日前宣布投产晶圆代工龙头2奈米制程 的公司(这意指超微AMD)。尽管公司未公布合作细节，供应链则透露，公司技术将应用在PC或游 戏机芯片，最快2027年可以看到产品上市。 国内封测厂多年来一直在推行FOPLP案，至今约莫9年，但一直没有看到有太多终端应用落地，主 要是因为起初因良率问题而迟迟未见显著成效，客户端态度也相对观望。再加上，早前应用层次停 留在RF IC、PMIC等相对成熟领域，如今在台积电(2330)登高一呼下，封测厂也加速转往消费性 电子、AI等更多元的应用场域。 谢永达表示，力成的FOPLP 技术自2016 年量产以来，当时技术相对简单，经过历年来的持续优 化，目前朝异质整合发展，规格主要采510X515 毫米。他也强调，目前全球真正具大规模FOPLP 生产能力的业者仅有公司一家，良率也大幅超出预期，现正与与一家美国客户合作验证中。 关 注 ...

Core Viewpoint - NVIDIA's next-generation Rubin AI architecture will utilize the company's first SoIC packaging, indicating a significant shift in the hardware market with the integration of advanced components like HBM4 [1][5] Group 1: SoIC Packaging Development - TSMC is rapidly constructing factories in Taiwan to shift focus from advanced packaging (CoWoS) to SoIC, with expectations for NVIDIA, AMD, and Apple to release next-generation solutions based on this design [1][2] - SoIC allows for the integration of different chips, reducing internal circuit layout space and lowering costs, with AMD being an early adopter and Apple expected to follow with its M5 chip [2][3] - TSMC's SoIC production capacity is projected to reach 15,000 to 20,000 wafers by the end of this year, with plans to double that capacity next year [2][6] Group 2: NVIDIA's Rubin Architecture - The Rubin GPU will separate the GPU and I/O die, utilizing N3P and N5B processes respectively, and will integrate these components using SoIC packaging [2][5] - The Vera Rubin NVL144 platform is expected to deliver up to 50 PFLOPS of FP4 performance with 288 GB of HBM4 memory, while the NVL576 will provide up to 100 PFLOPS and 1 TB of HBM4e capacity [5] Group 3: Workforce and Production Adjustments - TSMC plans to adjust its workforce from 8-inch fabs to support advanced packaging facilities, aiming to recruit 8,000 new employees this year to reach a target of 100,000 [3] - The company is actively preparing for the integration of SoIC technology, which is seen as crucial for future developments in semiconductor packaging [3][6]