Core Viewpoint - The article discusses the evolution and significance of TSMC's CoWoS packaging technology, particularly in relation to NVIDIA's increasing reliance on CoWoS-L for its Blackwell architecture, highlighting the challenges and advancements in the semiconductor industry [1][2][5]. Group 1: TSMC and NVIDIA Collaboration - TSMC has become a crucial partner for NVIDIA, especially in the CoWoS packaging technology, with NVIDIA's CEO stating that they have no alternative to TSMC for this advanced technology [1]. - TSMC has reportedly surpassed ASE Group to become the largest player in the global packaging and testing market, driven by the demand for advanced packaging solutions [1]. Group 2: CoWoS Technology Evolution - NVIDIA plans to increase the use of CoWoS-L packaging for its upcoming Blackwell series products, transitioning from CoWoS-S to meet the high bandwidth requirements of its GPUs [2]. - The CoWoS technology faces challenges due to the increasing chip sizes, which limit the number of chips that can be placed on a 12-inch wafer, and the associated thermal management issues [5]. Group 3: Innovations and Challenges - TSMC is exploring the use of flux-free bonding technology to address issues related to flux residue that can affect chip reliability, with testing expected to be completed by the end of the year [6]. - The current interposer size in TSMC's CoWoS packaging is 80x80mm, with plans to introduce larger sizes by 2026 and 2027, which may enhance performance but also pose design challenges [8]. Group 4: Future Technologies - TSMC is betting on CoPoS technology, which replaces the traditional wafer with a panel, allowing for greater chip density and efficiency, with plans for mass production by 2029 [9][10]. - CoPoS is positioned as a potential alternative to CoWoS-L, offering advantages in signal integrity and power transmission, particularly for high-performance applications [11]. Group 5: Market Implications - The shift from circular wafers to square panels in CoPoS technology is expected to significantly enhance production capacity and cost efficiency, making it competitive in AI, 5G, and high-performance computing sectors [12]. - Despite the advantages, the transition to CoPoS requires substantial investment in materials and equipment, and overcoming technical challenges related to precision and yield will be critical for its success [13].

Core Viewpoint - The article discusses the significant advancements and challenges in TSMC's CoWoS (Chip-on-Wafer-on-Substrate) packaging technology, particularly in relation to NVIDIA's evolving needs in the AI sector, highlighting the shift towards CoWoS-L and the emergence of CoPoS (Chip-on-Panel-on-Substrate) as a potential alternative [1][3][11]. Group 1: TSMC and NVIDIA Collaboration - TSMC has become a crucial partner for NVIDIA, especially in the CoWoS technology, with NVIDIA's CEO stating that they have no alternative to TSMC in this area [1]. - NVIDIA is transitioning to use more CoWoS-L packaging for its upcoming Blackwell series products, which require high bandwidth interconnects [3][6]. Group 2: CoWoS Technology Developments - TSMC has been expanding its CoWoS capacity significantly over the past two years and is reportedly surpassing ASE Group to become the largest packaging player globally [1]. - The CoWoS technology is evolving, with TSMC planning to introduce CoWoS-L with a mask size of 5.5 times by 2026 and a record 9.5 times by 2027 [9]. Group 3: Challenges in CoWoS Technology - The increasing chip sizes pose challenges for CoWoS packaging, as larger chips reduce the number of chips that can fit on a 12-inch wafer [6]. - TSMC is facing difficulties with flux usage in CoWoS, which is essential for chip bonding, and is exploring flux-free bonding technologies [7][9]. Group 4: Emergence of CoPoS Technology - CoPoS technology is being developed as a next-generation alternative to CoWoS, allowing for higher chip density and efficiency by using a panel instead of a wafer [11][14]. - TSMC's AP7 factory is set to become a key hub for advanced packaging, focusing on CoPoS production [12]. Group 5: Comparison of FOPLP and CoPoS - FOPLP (Fan-out Panel-Level Packaging) and CoPoS both utilize large panel substrates but differ in architecture and application, with CoPoS offering better signal integrity due to its use of an interposer [12][13]. - CoPoS is positioned for high-end applications in AI and HPC systems, while FOPLP is more suited for mid-range applications [13][14].

Core Viewpoint - The article discusses the significant advancements and challenges in TSMC's CoWoS (Chip-on-Wafer-on-Substrate) packaging technology, particularly in relation to NVIDIA's evolving needs in the AI sector, highlighting the shift towards CoWoS-L and the emergence of CoPoS (Chip-on-Panel-on-Substrate) as a potential alternative [1][3][10]. Group 1: TSMC and NVIDIA Collaboration - TSMC has become a crucial partner for NVIDIA, especially in the CoWoS domain, with NVIDIA's CEO Jensen Huang stating that they have no alternative to TSMC for this advanced packaging technology [1]. - NVIDIA is transitioning to use more CoWoS-L packaging for its latest Blackwell series products, which require high bandwidth interconnects between chips [3][5]. Group 2: CoWoS Technology Evolution - The CoWoS technology is facing challenges due to increasing chip sizes, with AI chips potentially reaching dimensions of 80x84 mm, limiting the number of chips per wafer [5]. - TSMC is exploring alternatives to traditional solder paste bonding methods due to difficulties in maintaining yield rates, including the development of no-solder paste bonding technology [6][9]. Group 3: Future Developments in Packaging - TSMC plans to introduce CoWoS-L with a mask size of 5.5 times the current size by 2026, and a record 9.5 times mask size CoWoS by 2027 [9]. - CoPoS technology is being developed as a next-generation packaging solution, with plans for mass production by 2029, aiming to enhance efficiency and reduce costs by utilizing larger rectangular substrates [12][14]. Group 4: Comparison of Packaging Technologies - CoPoS differs from FOPLP (Fan-out Panel-Level Packaging) in that it uses an interposer for better signal integrity and power delivery, making it suitable for high-performance applications [13]. - The transition from traditional organic substrates to glass substrates in CoPoS is expected to improve interconnect density and thermal stability, positioning it as a potential successor to CoWoS-L [14].

"宁波膜智信息科技有限公司"为势银（TrendBank）唯一工商注册实体及收款账户 添加文末微信，加 先进封装 群 Manz亚智科技积极推进CoWoS面板化概念，即CoPoS，以解决封装效率与芯片产能问题。目 前，Manz亚智科技的FOPLP技术已步入量产阶段，同时行业也在探索基于玻璃基板的封装方 案，以进一步提升封装效能，实现更高带宽、更大密度与更强散热性能。 势银研究： 势银产业研究服务 势银数据： 势银数据产品服务 势银咨询： 势银咨询顾问服务 重要会议： 4月29日，2025势银异质异构集成封装产业大会（浙江宁波） 点此报名 当前， 随着生成式人工智能（ Generative AI）的迅猛发展，高阶AI芯片需求呈爆发式增长， 材料和封装技术迎来新的变革契机。在此背景下，突破产能瓶颈，推动先进封装成为行业新焦 点。其中，Chip-on-Wafer-on-Substrate (CoWoS) 面板化方案──Chip-on-Panel-on- Substrate (CoPoS) 概念正引领未来技术发展方向。 由此，势银（TrendBank）访谈了亚智科技事业开发部副总经理简伟铨，深入交流了当下产业 发展现状以 ...

Core Viewpoint - The article discusses the shift in advanced semiconductor packaging towards Fan-Out Panel Level Packaging (FOPLP), which is expected to replace CoWoS as the new mainstream for AI chip packaging. Innolux, leveraging its existing panel production advantages, aims to mass-produce FOPLP by mid-2023, outpacing major semiconductor players like TSMC and ASE Group [1][3]. Group 1: Industry Trends - FOPLP technology is gaining traction due to its higher chip placement efficiency and lower costs compared to traditional CoWoS, which uses circular substrates. The square substrates in FOPLP allow for a greater number of chips to be packaged, significantly improving utilization rates [3][4]. - Major companies, including TSMC and ASE Group, are also exploring FOPLP technology, with ASE Group planning to enter the 600mm x 600mm FOPLP space by Q2 2023 and begin trial production in Q3 2023 [3][4]. Group 2: Company Strategy - Innolux has been developing FOPLP technology for eight years and has launched a "Semiconductor Fast Track Plan" to recruit 500 new talents to accelerate its deployment and achieve mass production of the largest FOPLP size of 700mm x 700mm by mid-2023 [4]. - The company has outlined a three-step roadmap for FOPLP technology, starting with Chip First process technology, followed by RDL First for mid-to-high-end products within 1-2 years, and TGV process technology in collaboration with partners expected to be ready in 2-3 years [4]. Group 3: Financial Outlook - Analysts are optimistic about Innolux's panel business, which is experiencing price increases despite the traditional off-season, and the advanced packaging segment is expected to yield higher profit margins than the panel business, thus reducing the risks associated with panel market fluctuations [1][3].