编者荐语： 眼下股市行情正好，没上市的公司瞧着上市同行的光景，心里头自然是又羡慕又眼馋…… 以下文章来源于芯评气和 ，作者芯评气和 芯评气和 . 集成电路(IC)、半导体、EDA深度原创媒体。专注于行业分析、芯片评测、技术分享。 推荐公众号可以关注↓ 一提到北京的上市公司，最多的还是金融业和IT行业，北京作为国内 IT 产业的核心聚集地，互联网、 软件服务、数字经济等领域的上市公司数量与体量均居全国前列，百度、字节跳动（拟上市）、小米等 企业构筑起庞大的数字产业生态。但在集成电路设计（IC design）领域，与上海、深圳相比，上市公司 阵容确实显得相对单薄。 摩尔线程 智能科技（北京 ）股份有限公司 于 2024 年 11 月 12 日在北京证监局办理辅导备案登记，正 式启动 A 股上市进程。该公司专注于研发设计全功能 GPU 芯片及相关产品，虽构建了智算产品线，但 在上市之路上，要应对行业内英伟达等巨头的激烈竞争，以及自身技术生态完善、市场份额提升等诸多 挑战 。 北京奕斯伟计 算技术股份 有限公司 于 2025 年 5 月 30 日向港交所递交招股书。聚焦智能终端与具身智 能两大核心应用场景，虽在 RI ...

一、ETF行业快讯 1.三大指数涨跌互现，多只农业板块ETF上涨 今日，三大指数涨跌互现，上证综指下跌0.39%，深证成指上涨0.26%，创业板指下跌0.76%。多只农业 板块ETF上涨，其中，农业ETF易方达（562900.SH）上涨2.94%，农业ETF（159825.SZ）上涨2.90%， 农业50ETF（516810.SH）上涨2.85%。电子板块多只ETF下跌，人工智能ETF科创（588760.SH）下跌 3.35%，科创芯片设计ETF（588780.SH）下跌3.10%，科创板人工智能ETF（588930.SH）下跌2.69%。 2.国内ETF规模突破5万亿元 据中国证券报，Wind数据显示，截至8月25日，境内ETF总规模首度突破5万亿元大关，创历史新高，达 到5.07万亿元。其中，股票型ETF、跨境ETF、债券型ETF、商品型ETF、货币型ETF最新规模分别为 3.46万亿元、7537.23亿元、5559.03亿元、1532.57亿元、1424.70亿元。 3.权益类ETF规模年内增长超24% 据证券日报，国内权益类ETF市场迎来里程碑时刻。Wind资讯数据显示，截至8月25日，全市场1188 ...

公众号记得加星标⭐️，第一时间看推送不会错过。 来源 ：内容转自知乎，作者 ：Dio-晶，谢谢 。 TPU7，你也想要吗？ 还记得上半年Google的TPU7的发布，Ironwood，号称与B200相匹敌。各项指标看上去，也确实称 得上炸裂。 为什么google行，我就不行？ 所以到今天，北美&东亚凡是能排得上号OTT，谁要是不自研芯片反而会被人觉得萎了。 想想也是，一个个都是搅动人类社会转速的巨棍了，那面对AI的FOMO，用卡是必须尽早、管饱才能 安心的，而内部算法团队也想要用算法+硬件高效协同来弯道超车DeepSeek甚至某一天形成壁垒的呼 声也越来越强烈，但现实中却又是不得不不定期kiss 黄'ass来排队买GPU，而且还往往不能保证供应 时间和可靠，想象一下都挺受罪的。 但话说回来，真正能说得上做得好的，能用管够，还能真正和Huang扳手腕的，目前只有Google TPU了，而且整整做了七代。你是不是真的也行？ 作为做芯片的一根老混子，但经历得多了，反而越发有些保守和迷信 ：） 到底应该怎么做？是什么 样的条件决定了成败？ 越深想，越觉得，得做颗AI芯片可能没那么难，但其实也没那么简单，难度 搞不好， ...

8月25日晚间，汇顶科技（603160）披露公告称，公司总裁柳玉平于8月22日收到证监会下发的《立案 告知书》，因涉嫌内幕交易，证监会决定对柳玉平进行立案。 版权声明 证券时报各平台所有原创内容，未经书面授权，任何单位及个人不得转载。我社保留追 究相关 行 为主体 法律责任的权利。 转载与合作可联系证券时报小助理，微信ID：SecuritiesTimes 汇顶科技表示，本次立案系针对柳玉平个人，与公司日常经营管理和业务活动无关，不会对公司及子公司 生产经营活动产生影响。立案调查期间，柳玉平将积极配合 证监会的立案 调查工作。 公开资料显示， 柳玉平 出生于1979年。其于 2005年3月加入汇顶科技，历任研发工程师、项目经理、 质量部经理、工程部总监等职；2015年1月至2022年5月期间，先后担任副总裁、供应链负责人、产品线 负责人等职务。 据报道，作为一家芯片设计公司，汇顶科技以屏下指纹识别技术见长，巅峰时 股价一度超385元/股 ，市 值一度超过中芯国际 。 然而，近年来，汇顶科技正面临着竞争对手迅速崛起以及业务转型的多重挑战。 8月21日，汇顶科技披露2025年半年度报告。公司上半年实现营业收入22. ...

"我认为台积电是人类历史上最伟大的公司之一，任何想购买台积电股票的人都是非常明智 的人。" AI播客：换个方式听新闻 下载mp3 音频由扣子空间生成 英伟达首席执行官黄仁勋对台积电(TSM.N)大加赞赏，表示任何希望入股该公司的投资者都是"非常明 智的"。作为全球最大的晶圆代工企业，台积电股价今年以来已上涨超过15%。 黄仁勋目前正在访问我国台湾地区，他乘坐私人飞机抵达，并补充说自己只会停留几个小时，与台积电 高层共进晚餐后就会离开。 黄仁勋表示，他此行是为了感谢台积电，因为该公司已为英伟达完成六款全新芯片的设计定稿，包括一 款新的GPU和一款用于英伟达下一代"Rubin"架构超级计算机的硅光子处理器。芯片设计最终定稿后， 就会进入量产准备阶段。 "这是我们公司历史上第一次所有芯片都全新且具有革命性。"他说，"我们已经完成了所有芯片的设计 定稿。"他明确表示： 此外，黄仁勋表示，英伟达迫切希望启动"英伟达星座"（NVIDIA Constellation）项目。这是该公司在 台湾地区新设立的一处办公地点，用于容纳不断扩大的台湾员工团队。 他说，公司正在与当地协商一些问题，以便尽快开工建设。"我们在台湾有很多很多 ...

Core Viewpoint - The article provides a comprehensive overview of the chip design process, emphasizing its complexity and the various stages involved in transforming electronic systems into physical integrated circuits. It highlights the importance of both front-end and back-end design, as well as the tools and methodologies used in the industry. Group 1: Basic Concepts of Chip Design - Chip design is a crucial pre-step in chip manufacturing, involving multiple stages of collaboration and strict validation [8][11] - The design process can be categorized into digital chip design and analog chip design, with a focus on digital chip design in this article [11] - The design hierarchy includes system level, register transfer level (RTL), gate level, transistor level, layout level, and mask level [11][12] Group 2: Chip Design Process - The chip design process consists of four main stages: specification design, system design, front-end design, and back-end design [25][21] - The current mainstream approach is top-down design, starting from system-level design and moving to RTL design [24] - The output of the design process includes specifications, design plans, netlists, layouts, and masks [21][23] Group 3: Front-End Design - Front-end design focuses on converting functional requirements into realizable circuit logic, ensuring functional correctness without considering physical implementation details [29] - Key steps in front-end design include HDL coding, simulation verification, logic synthesis, static timing analysis, and formal verification [52][60][68] - Tools used in front-end design include HDL simulators, logic synthesis tools, and static timing analysis tools [28] Group 4: Back-End Design - Back-end design is based on the netlist obtained from front-end design, focusing on creating the physical layout [72] - Key steps in back-end design include layout planning, physical layout, clock tree synthesis, routing, and physical verification [72][76][97] - The final output of back-end design is the GDSII file, which is used for manufacturing the chip [108] Group 5: Market and Industry Insights - The global chip design market is expected to grow at a compound annual growth rate (CAGR) of 9.8% from 2020 to 2024, with the market size surpassing $480 billion by 2024 [39] - The share of the Chinese market in chip design is rapidly increasing, rising from 19% to 28% [39] - Major players in the EDA industry include Synopsys, Cadence, and Siemens EDA, which collectively hold over 70% market share [38]

Financing Overview - The recent financing round was led by the China Internet Investment Fund, with participation from OPPO, Changjiang Securities, and Huaye Tiancai among others [2] - Previous investors include Huawei's Hubble Technology, Xiaomi's Changjiang Industrial Fund, and ByteDance's Quantum Leap [2] Company Profile - Juxin Microelectronics, established in 2016, focuses on high-performance analog and mixed-signal chip design, headquartered in Wuhan Optics Valley [6] - The company has R&D centers in Europe, Beijing, Shenzhen, Shanghai, and Suzhou [6] - Juxin's self-developed back-illuminated high-resolution 3D-iToF sensor chips, under-display optical sensor chips, and multispectral sensing chips are widely used in high-end mobile phones and tablets [6] - The company ranks first in domestic shipments of optical sensing and 3D optical chips, and is among the top three in smart audio chip shipments [6] Leadership - The founder and chairman, Liu Deheng, is a native of Wuhan and holds a degree in Electronic and Information Engineering from Huazhong University of Science and Technology [7] - Liu has pursued further studies at prestigious institutions such as Tohoku University in Japan, Delft University of Technology in the Netherlands, and Virginia Tech in the United States, and previously worked at a leading semiconductor company in the Netherlands with a high salary [7]

Core Viewpoint - Beijing Jichuang Beifang Technology Co., Ltd. (referred to as "Jichuang Beifang") has initiated the IPO counseling registration for the Sci-Tech Innovation Board on August 5, 2023, with CITIC Securities as the counseling institution. The company previously withdrew its IPO application in March 2023 after being accepted in June 2022, aiming to raise 60.10 billion yuan for various projects, including the development and industrialization of display touch integrated chips [1][3]. Company Overview - Jichuang Beifang was established on September 3, 2008, with a registered capital of 431.065156 million yuan. The company is primarily controlled by Zhang Jinfang, who holds a 39.97% stake through direct and indirect holdings [2][9]. - The company specializes in the research, design, and sales of display chips, having achieved leading market shares in various segments, including display driver chips and power management chips [5][6]. Market Position - Jichuang Beifang ranks first among Chinese manufacturers in the global smartphone LCD display driver chip and LCD/TDDI chip markets. It is also the second-largest in the large-size LCD panel display driver chip market in China [6]. - The company has been recognized as a national-level manufacturing champion and has participated in significant events such as the 70th anniversary of the victory in the War of Resistance, the 100th anniversary of the Communist Party, and the Beijing Winter Olympics [5][6]. Financial Performance - In 2021, Jichuang Beifang reported nearly 5.643 billion yuan in revenue and a net profit of 930 million yuan. The company's revenue has shown significant growth from 1.447 billion yuan in 2019 to 5.674 billion yuan in 2021 [8][7]. - The company's asset-liability ratio decreased from 39.40% in 2019 to 30.93% in 2021, indicating improved financial stability [8]. Investment and Shareholding - Jichuang Beifang has attracted investments from various notable institutions, including state-owned capital and private equity funds. Major shareholders include Beijing Yizhuang Strategic Emerging Industry Fund and other private equity firms [12][14]. - The company completed its E-round financing in 2021, raising 6.5 billion yuan, which significantly increased its valuation to 314.35 billion yuan [14]. Industry Comparison - Jichuang Beifang's peers in the A-share market, such as OmniVision Technologies and Geke Microelectronics, are also experiencing revenue and profit growth, indicating a positive trend in the display chip industry [16][17].

Core Viewpoint - Jensen Huang, CEO of Nvidia, expressed confidence in China's AI market growth, stating that it will continue to thrive regardless of Nvidia's presence, which challenges the skepticism surrounding China's technological potential [1][5]. Group 1: Nvidia's Position and China's Technological Landscape - Huang highlighted Huawei's technological achievements, noting its capabilities in autonomous driving and AI, as well as its strong chip design and system software skills, suggesting that Chinese companies can sustain the market even without Nvidia [3][5]. - The complexity and efficiency of China's supply chain were praised by Huang, emphasizing its significant role in the global supply chain and its ability to support various industries [3][5]. Group 2: U.S. Government Policies and Their Impact - Huang criticized the U.S. government's strategy of restricting semiconductor exports to China, arguing that such measures are self-deceptive and may ultimately harm U.S. interests by spurring innovation in China [5][7]. - Despite the U.S. government's attempts to limit China's technological advancement, negotiations between the U.S. and China are reportedly ongoing, indicating a complex relationship where both sides are navigating trade discussions while imposing restrictions [5][7]. Group 3: Future of U.S.-China Relations and Global Innovation - Huang asserted that the ongoing technological competition between the U.S. and China is a focal point, with China possessing ample innovation spirit and technical capability that cannot be fundamentally hindered by U.S. restrictions [7][9]. - The need for open markets and collaborative technological exchanges was emphasized as a pathway to mutual benefits, highlighting that both nations must adopt a more open and pragmatic approach to face future challenges [9].

Core Viewpoint - The article discusses the shift towards "highly customized" chip design driven by advancements in technologies such as AI, large models, intelligent driving, and the Internet of Things, highlighting the challenges and solutions in the context of K library characterization for non-standard cells [1][20]. Group 1: Customization in Chip Design - The traditional model of using standard cells for large-scale chip design is no longer sufficient to meet the increasingly refined and scenario-specific design requirements [1]. - Design teams are increasingly incorporating non-standard/custom cells to achieve better balance among area, power consumption, and performance [1][3]. - The introduction of non-standard cells, such as high-speed CDC modules and pulse latches, allows for targeted system optimization but also raises new challenges in EDA tool modeling capabilities [1][3]. Group 2: K Library Characterization - K library characterization is crucial for ensuring design progress and product reliability, acting as an "invisible engine" in the chip development process [1]. - K library serves as a "genetic map" that provides real physical behavior to standard cells through high-precision simulations, extracting key parameters like timing, power consumption, and noise [2]. - The complexity of non-standard cells necessitates advanced modeling techniques, as any minor deviation can lead to significant timing issues in subsequent designs [5][9]. Group 3: Specific Non-Standard Cells - High-speed CDC units are essential for ensuring safe and reliable data transmission across different clock domains, addressing metastability issues [3]. - Pulse latches utilize narrow pulses for data storage, significantly reducing power consumption, but require precise control of pulse width to avoid data storage errors [5][7]. - Dynamic registers, which store states using capacitors, present challenges in K library extraction due to their sensitivity to noise and the need for regular state updates [9]. Group 4: Liberal's Solutions - The Liberal product from Huada Jiutian offers a comprehensive K library solution, addressing the challenges of custom non-standard cell characterization with high efficiency and precision [2][15]. - Liberal's tools provide accurate simulation incentives and consider various noise factors, ensuring the accuracy of K library models [15][17]. - The introduction of Liberal has significantly improved efficiency and quality in K library extraction for high-performance chip designs, leading to timely delivery and high customer satisfaction [19]. Group 5: Future Outlook - As non-standard designs become more common with advancing process nodes, Liberal aims to continue enhancing K library extraction technology towards greater intelligence, efficiency, and precision [20].